MC68030RC33C Freescale Semiconductor, MC68030RC33C Datasheet - Page 289

• Manufacturer Part Number: MC68030RC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

8
8-22
8.1.11 Breakpoint Instruction Exception
To use the MC68030 in a hardware emulator, it must provide a means of
tor base register on the MC68010, MC68020, and MC68030 allows arbitrary
the execution of a program residing in the on-chip instruction cache without
severe performance degradation.
When the MC68030 executes a breakpoint instruction, it performs a break-
for the CPU space type $0 addresses and to 7.4.2
Cycle
The processor copies the status register, enters the supervisor privilege level,
value (which points to the next instruction), and the copy of the status register
vector.
inserting breakpoints in the emulator code and of performing appropriate
operations at each breakpoint. For the MC68000 and MC68008, this can be
done by inserting an illegal instruction at the breakpoint and detecting the
illegal instruction exception from its vector location. However, since the vec-
relocation of exception vectors, the exception address cannot reliably identify
a breakpoint. The MC68020 and MC68030 processors provide a breakpoint
capability with a set of breakpoint instructions, $4848-$484F, for eight unique
breakpoints. The breakpoint facility also allows external hardware to monitor
point acknowledge cycle (read cycle) from CPU space type $0 with address
lines A2-A4 corresponding to the breakpoint number. Refer to Figure 7-44
word on the data bus. If the bus cycle terminates with BERR, the processor
with DSACKx or STERM, the processor uses the data returned to replace the
of that instruction. The remainder of the pipe remains unaltered. In addition,
and clears the trace bits. The processor saves the vector offset, the scanPC
on the supervisor stack, it also saves the logical address of the PMOVE
instruction on the stack. Then the processor resumes normal instruction
execution after the required prefetches from the address in the exception
hardware can return either BERR, DSACKx, or STERM with an instruction
performs illegal instruction exception processing. If the bus cycle terminates
breakpoint instruction in the internal instruction pipe and begins execution
no stacking or vector fetching is involved with the execution of the instruction.
Figure 8-7 is a flowchart of the breakpoint instruction execution.
for a description of the breakpoint acknowledge cycle. The external
MC68030 USER'S MANUAL
Breakpoint Acknowledge
MOTOROLA