MC68030RC33C Freescale Semiconductor, MC68030RC33C Datasheet - Page 297

• Manufacturer Part Number: MC68030RC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

3
8-30
To repair data faults (indicated by DF= 1), the software should first examine
the RM bit in the SSW to determine if the fault was generated during a read-
the data output buffer (DOB) on the stack frame to the location indicated by
the data fault address in the address space defined by the SSW. (Both the
and the handler must transfer properly sized data from the location indicated
3-byte operands are right-justified in the 4-byte data buffers. In addition, the
software handler must clear the DF bit of the SSW to indicate that the faulted
the operation word at the program counter address (SP + 2 of the stack frame).
This is true even if the fault occurred on the first read cycle.
the handler reads and modifies (if necessary) the memory location. It clears
the DF bit in the SSW of the stack frame and modifies the condition codes
of the SSW to determine if the fault was caused by a read or a write cycle.
DOB and the data fault address are part of the stack frame at SP+$18 and
SP + $10, respectively.) Data read faults only generate the long bus fault frame
by the fault address and address space to the image of the data input buffer
(DtB) at location SP+$2C of the long format stack frame. Byte, word, and
bus cycle has been corrected.
To emulate a read-modify-write cycle, the exception handler must first read
This word identifies the CAS, CAS2, or TAS instruction that caused the fault.
Then the handler must emulate this entire instruction (which may consist of
status register appropriately, because the RTE instruction expects the entire
operation to have been completed if the RM bit is set and the DF bit is cleared.
To emulate the entire instruction, the handler must save the data and address
should not modify a bus fault stack frame. The only bits in the SSW that may
Address error faults must be repaired in software. Address error faults can
modify-write operation. If RM =0, the handler should then check the R/W bit
For data write faults, the handler must transfer the properly sized data from
up to four long word transfers) and update the condition code portion of the
registers for the instruction (with a MOVEM instruction, for example). Next,
in the status register copy and the copies of any data or address registers
required for the CAS and CAS2 instructions. Last, the handler restores the
registers that it saved at the beginning of the emulation. Except for the data
input buffer (DIB), the copy of the status register, and the SSW, the handler
be modified are DF, RB, and RC; all other bits, including those defined for
internal use, must remain unchanged.
be distinguished from bus error faults by the value in the vector offset field
of the format word.
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