MC68MH360VR33L Freescale Semiconductor, MC68MH360VR33L Datasheet - Page 97

• Manufacturer Part Number: MC68MH360VR33L
• Description: IC MPU QUICC 33MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360VR33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Step 13. Initialize the time slot assignment tables, TSATTx and TSATRx. Each valid entry
should have the V bit set. Clear the W bit in all entries except the last entry in the table. The
‘mask’ bits determine which bits of the time slot are processed by the CPM–normally set
to 0xFF to process all 8 bits. The 6-bit CP field holds the most-significant bits of the starting
address of the channel-specific parameter area. For the MH360, the most-significant bit
must be zero. The 6 least-significant bits are always cleared. See Section 2.1.3, “TSATRx/
TSATTx Pointers and Time Slot Assignment Table,” for more information. The following
is example pseudocode for TSA table programming:
for (x = 0; x < time slots; x++)
{
}
Step 14. Initialize TSAT pointers (Tx_S_PTR and Rx_S_PTR), and the current time slot
entry pointers, (RxPTR and TxPTR). Initialize both Tx_S_PTR and TxPTR to the first
entry of the TSATx. Also initialize both Rx_S_PTR and RxPTR to the first entry of the
TSARx. For common Rx and Tx time slot assignment tables, they all should point to SCC
base + 20; however, they may be located anywhere within the dual-ported RAM. See
Section 2.1.3, “TSATRx/TSATTx Pointers and Time Slot Assignment Table,” for more
information. The following is an example configuration:
Step 15. Initialize multichannel controller state QMC-STATE to 0x8000.
SCC1.TSATR[x].W = 0;
SCC1.TSATR[x].CP = x;
SCC1.TSATR[x].mask0_1 = 3;
SCC1.TSATR[x].mask2_7 = 0x3F; /* no subchanneling */
SCC1.TSATR[x].V = 1;
SCC1.TSATR[last].W = 1;
SCC1.Tx_S_PTR = SCC1.MCBASE+0x20;/* init pointer to TSATTx table */
SCC1.TxPTR = SCC1.Tx_S_PTR;
SCC1.Rx_S_PTR = SCC1.MCBASE+0x20;/* init pointer to TSATRx table */
SCC1.RxPTR = SCC1.Rx_S_PTR;
pdpr->SCC1.QMC_STATE = 0x8000;
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Chapter 6. QMC Initialization
/* not last time slot */
/* mark channel number */
/* no subchanneling */
/* mark time slot valid */
/* last time slot wrap */