MC68MH360VR33L Freescale Semiconductor, MC68MH360VR33L Datasheet - Page 19

• Manufacturer Part Number: MC68MH360VR33L
• Description: IC MPU QUICC 33MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360VR33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

1.3 QMC Features
• MC68MH360-specific features
• MPC860MH/DH-specific features
• Common features
• Serial interface
— Up to 32 independent communication channels
— Arbitrary mapping of any of 0–31 channels to any of 0–31 TDM time slot
— Can support arbitrary mapping of any of 0–31 channels to any of 0–63 TDM time
— Up to three additional HDLC 64-Kbps channels at 25-MHz system clock
— Simultaneous Ethernet support at 33-MHz system clock
— Up to 64 DMA channels with linear buffer array
— Up to 64 independent communication channels
— Arbitrary mapping of any of 0–63 channels to any of 0–63 TDM time slots
— Supports arbitrary mapping of any of 0–63 channels to any of 0–127 TDM time
— Two simultaneous 32-channel E1 links at 50-MHz system clock
— Up to 128 DMA channels with linear buffer array
— Independent mapping for receive/transmit
— Supports either transparent or HDLC protocols for each channel
— Interrupt circular buffer with programmable size and overflow identification
— Global loop mode
— Individual channel loop mode through the SI
— Programmable frame length (via SI)
— Serial-multiplexed (full duplex) input/output 2048-, 1544-, or 1536-Kbps PCM
— Compatible with T1/DS1 24-channel and CEPT E1 32-channel PCM highway,
— Subchanneling on each time slot
— Allows independent transmit and receive routing, frame syncs, and clocking
— Concatenation of any, not necessarily consecutive, time slots to channels
— Supports H0, H11, and H12 ISDN channels
— Allows dynamic allocation of channels
slots in case of common Rx and Tx mapping
slots in case of common Rx and Tx mapping
highways
ISDN basic rate, ISDN primary rate and user-defined
independently for receive/transmit
Freescale Semiconductor, Inc.
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Chapter 1. Overview