MC68MH360VR33L Freescale Semiconductor, MC68MH360VR33L Datasheet - Page 52

• Manufacturer Part Number: MC68MH360VR33L
• Description: IC MPU QUICC 33MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360VR33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

0
1
2
3
4
5
6
7
8–9
10–11
12–15
Field
MODE
RD
—
ENT
—
SYNC
RES
POL
—
—
—
Name
Mode—Each channel has a programmable option whether to use transparent mode or HDLC
mode.
0 Transparent mode
1 HDLC mode
Reverse data
0 The bit order will not be reversed, transmitting/receiving the LSB of each octet first.
1 The bit order as seen on the channels is reversed, transmitting/receiving the MSB of each
1
Enable transmit
0 Disable transmitter. If this bit is cleared and the channel’s transmitter is routed to a certain
1 The transmit portion of the channel is enabled and data is sent according to protocol and to
Reserved
Synchronization—Controls synchronization of multichannel operation in transparent mode.
0 The first byte is put in the first available time slot or is read from the first available time slot to
1 The synchronization algorithm according to TRANSYNC is done.
Reserved
Enable polling—Enables the transmitter to poll the transmit BDs.
0 The CPM will not check the ready (R) bit in the transmit buffer descriptor.
1 The CPM will go check the ready (R) bit in the transmit buffer descriptor.
The user can use this bit to prevent unnecessary external bus cycles when checking the ready
bit (R) in the buffer descriptor. Software should always set POL at the beginning of a transmit
sequence of one or more frames. The RISC processor clears POL (0) when no more buffers are
ready in the transmit queue when it finds a buffer descriptor with the R bit cleared (0), that is, at
the end of a frame or at the end of a multiframe transmission. To prevent deadlock, software
should prepare the new BD, or multiple BDs, and set (1) the ready (R) bit in the BD before setting
(1) POL.
Note that the CPM automatically clears this bit; the user should never try to clear this bit in
software.
0
Reserved
0
Table 2-11. CHAMR Bit Settings (Transparent Mode)
octet first.
time slot (within TSATTx, see Figure 2-3) the transmitter sends 1’s on this time slot.
other control settings.
this logical channel.
Freescale Semiconductor, Inc.
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QMC Supplement
Description