MC68MH360VR33L Freescale Semiconductor, MC68MH360VR33L Datasheet - Page 153

• Manufacturer Part Number: MC68MH360VR33L
• Description: IC MPU QUICC 33MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360VR33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

A
Acronyms and abbreviations, xiii
Alignment
B
Bibliography of additional reading, xii
Bit numbering, MC68360, A-1
Buffer descriptor
Bus latency and peak load, 8-5
C
Channel
Circular interrupt table, external memory, 4-1
Commands
Configuration difficulties, MC68MH360, 5-20
Conventions, xii
CPM loading, 8-2
D
Data clock generation, C-4
Disabling receiver/transmitter, 6-17
E
E1/T1 frame description, 1-11
non-octet alignment data, 5-4
buffer descriptor tables, 2-4
data buffer pointer, 2-5
placement, 5-7
RxBD, 5-1
TxBD, 5-5
channel addressing capability, 1-2
channel pointers
channel-specific parameters, 2-14, 6-18
channel-specific transparent parameters, 2-20
common combinations, 8-1
interrupt processing flow, 4-7
interrupt table entry, 4-5
receive, 3-2
transmit, 3-1
MCBASE, 2-4
RBASE, 2-4
TBASE, 2-4
time slot assignment, 2-4
TSATRx, 2-9
TSATTx, 2-9
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INDEX
Index
Echo mode, 1-5
Errors
Ethernet
Exceptions
F
Features
Frame sync generation, C-4
Frequently asked questions (FAQ), B-1
G
Global error events
Global multichannel parameters, 2-5, 6-18
Global overrun, 4-3
Global underrun, 4-3
I
Interrupt table entry, 4-5, A-3, A-4
Inverted signals, 1-5
ISDN connection to QUICC32, C-1
L
Latency
Loading
Loopback mode, 1-5
global error events, 4-2
SI RAM, 1-10
MC68MH360 configuration, 5-20
routing examples, 1-6–1-9
channel interrupt processing flow, 4-7
interrupt table entry, 4-5
overview, 4-1
TxB, 5-6
deleted, 7-1
summary, list, 1-3
description, 4-2
restart, 4-3, 6-17
bus latency and peak load, 8-5
simulated latencies, 8-6
CPM loading, 8-2
peak load and bus latency, 8-5