MC68MH360VR33L Freescale Semiconductor, MC68MH360VR33L Datasheet - Page 154

• Manufacturer Part Number: MC68MH360VR33L
• Description: IC MPU QUICC 33MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360VR33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

M
MC68MH360 ethernet configuration, 5-20
Memory
Multichannel parameters and SCC base, 2-3
Multi-subchannel microcode (MSC)
N
Nonmulitplexed serial interface (NMSI) mode, 1-4
P
Parameters
Peak load and bus latency, 8-5
Performance issues, 8-1
Pointers
circular interrupt table, external memory, 4-1
internal memory structures
memory organization, 2-1
memory structure, 2-2
QMC memory organization, 9-7
features list, 9-1
initialization, 9-8
operation, 9-2
programming the MSC protocol, 9-3
subchanneling example, 9-6
channel-specific parameters, 2-14
HDLC parameters, 2-14
RAM usage over several SCCs, 5-9
SCC2 parameter RAM overlap (example), 5-8
transparent parameters, 2-20
channel pointers
data buffer, 2-5
pointer registers, 6-17
table pointers
MC68MH360, 2-1, 5-7
MPC860MH, 2-1, 5-14
MCBASE, 2-4
RBASE, 2-4
TBASE, 2-4
time slot assignment, 2-4
TSATRx, 2-9
TSATTx, 2-9
time slot assignment, 2-3
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
QMC Supplement
INDEX
Q
QMC
QUICC overview, 1-1
QUICC32 protocol, C-1
R
RAM
Registers
RISC processor, 9-1
Routing examples (serial), 1-6
channel addressing capability, 1-2
commands, 3-1
common channel combinations, 8-1
features list, 1-3
global parameters, 2-5
initialization, 6-1
MC68MH360 configuration, 5-20
protocol, 1-1, C-1
RAM usage over several SCCs, 5-9
routing table changes, 1-10
channel-specific parameters, 2-14
dual-ported base, 2-3
SCC2 parameter RAM overlap (example), 5-8
SI RAM errors, 1-10
command register, A-4
HDLC mode
pointer registers, 6-17
RxBD, A-5
SCC mask, A-5
SCCE, 4-3, A-5
state registers, 6-18
transparent mode
TxBD, A-5
CHAMR, 2-15, A-3
interrupt table entry, A-3
INTMSK, 2-18, A-3
RSTATE, 2-19, A-3
TSTATE, 2-17, A-3
CHAMR, 2-21, A-4
interrupt table entry, A-4
INTMSK, 2-24, A-4
RSTATE, 2-28, A-4
TRNSYNC, 2-24
TSTATE, 2-23, A-4