MC68MH360VR33L Freescale Semiconductor, MC68MH360VR33L Datasheet - Page 104

• Manufacturer Part Number: MC68MH360VR33L
• Description: IC MPU QUICC 33MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360VR33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

/* Continuous mode bits are initialized to 0 from reset */
/* Transmit data length field is initialized to 0 from */
/* reset; the Ready bit is also 0 from reset. */
/* Clear interrupt table */
};
chbd[0].recvbd0.rxbdptr = (char *)((int)chbd + 0x100);/*
pointer=0x100 */
chbd[1].recvbd0.rxbdptr = (char *)((int)chbd + 0x200);/*
pointer=0x200 */
chbd[2].recvbd0.rxbdptr = (char *)((int)chbd + 0x300);/*
pointer=0x300 */
chbd[3].recvbd0.rxbdptr = (char *)((int)chbd + 0x400);/*
pointer=0x400 */
for (v1 = 0; v1 < 4; v1++)
{
};
intrpt = pdpr->INTBASE;
for (v1 = 0; v1 < 10; v1++)
{
};
intrpt[9].W = 1;
poem[0] = "Humpty Dumpty sat on a wall\n\r";
poem[1] = "Humpty Dumpty had a great fall\n\r";
poem[2] = "All the king's horses and all the king's men\n\r";
pdpr->ch[v1].ZDSTATE = 0x80;
pdpr->ch[v1].INTMSK = 0xA;
pdpr->ch[v1].MFLR = 60;
pdpr->ch[v1].TBPTR = pdpr->ch[v1].TBASE;
pdpr->ch[v1].RBPTR = pdpr->ch[v1].RBASE;
chbd[v1].recvbd0.rxbdsac.E = 1;
chbd[v1].recvbd0.rxbdsac.W = 1; /*endreceive buffer descriptors */
chbd[v1].recvbd0.rxbdsac.I = 1;
chbd[v1].xmitbd0.txbdsac.W = 1;/* end xmit buffer descriptors */
chbd[v1].xmitbd0.txbdsac.I = 1;
chbd[v1].xmitbd0.txbdsac.L = 1;
chbd[v1].xmitbd0.txbdsac.TC= 1;
chbd[v1].xmitbd0.txbdcnt = 0;
intrpt[v1].V = 0;
intrpt[v1].W = 0;
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QMC Supplement
/* mark receive bufs empty */
/* enable intrpts */
/* enable intrpts */
/* last buffer in frame */
/* xmit CRC sequence */
/* clear data length field */
/* clear valid bits */
/* clear wrap bits */
receive
receive
receive
receive
BD0
BD1
BD2
BD3