MC68340AG16VE Freescale Semiconductor, MC68340AG16VE Datasheet - Page 92

• Manufacturer Part Number: MC68340AG16VE
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16VE

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

3.6.1 Bus Request
External devices capable of becoming bus masters request the bus by asserting BR . This
signal can be wire-ORed to indicate to the MC68340 that some external device requires
control of the bus. The MC68340 is effectively at a lower bus priority level than the
external device and relinquishes the bus after it has completed the current bus cycle (if
one has started). If no BGACK is received while the BR is active, the MC68340 remains
bus master once BR is negated. This prevents unnecessary interference with ordinary
processing if the arbitration circuitry inadvertently responds to noise or if an external
device determines that it no longer requires use of the bus before it has been granted
mastership.
3.6.2 Bus Grant
The MC68340 supports operand coherency; thus, if an operand transfer requires multiple
bus cycles, the MC68340 does not release the bus until the entire transfer is complete.
Therefore, assertion of BG is subject to the following constraints:
Externally, the BG signal can be routed through a daisy-chained network or a priority-
encoded network. The MC68340 is not affected by the method of arbitration as long as the
protocol is obeyed.
3.6.3 Bus Grant Acknowledge
An external device cannot request and be granted the external bus while another device is
the active bus master. A device that asserts BGACK remains the bus master until it
negates BGACK . BGACK should not be negated until all required bus cycles are
completed. Bus mastership is terminated at the negation of BGACK .
Once an external device receives the bus and asserts BGACK , it should negate BR . If BR
remains asserted after BGACK is asserted, the MC68340 assumes that another device is
requesting the bus and prepares to issue another BG .
MOTOROLA
• The minimum time for BG assertion after BR is asserted depends on internal
• During an external operand transfer, the MC68340 does not assert BG until after
• During an external operand transfer, the MC68340 does not assert BG as long as
• If the show cycle bits SHEN1–SHEN0 = 01, the MC68340 does not assert BG to
synchronization (see Section 11 Electrical Characteristics).
the last cycle of the transfer (determined by SIZx and DSACK ).
RMC is asserted.
an external master.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68340 USER’S MANUAL
Go to: www.freescale.com
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