MC68340AG16VE Freescale Semiconductor, MC68340AG16VE Datasheet - Page 228

• Manufacturer Part Number: MC68340AG16VE
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16VE

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor, Inc.
priority, many instruction words would be flushed unused, and necessary operand cycles
would be delayed. To maximize available bus bandwidth, the CPU32 will schedule a
prefetch only when the next instruction is not a change-of-flow instruction and when there
is room in the pipeline for the prefetch.
5.7.1.3.2 Write Pending Buffer. The CPU32 incorporates a single-operand write pending
buffer. The buffer permits the microsequencer to continue execution after a request for a
write cycle is queued in the bus controller. The time needed for a write at the end of an
instruction can overlap the head cycle time for the following instruction, thus reducing
overall execution time. Interlocks prevent the microsequencer from overwriting the buffer.
5.7.1.3.3 Microbus Controller. The microbus controller performs bus cycles issued by
the microsequencer. Operand accesses always have priority over instruction prefetches.
Word and byte operands are accessed in a single CPU-initiated bus cycle, although the
external bus interface may be required to initiate a second cycle when a word operand is
sent to a byte-sized external port. Long operands are accessed in two bus cycles, most
significant word first.
The instruction pipeline is capable of recognizing instructions that cause a change of flow.
It informs the bus controller when a change of flow is imminent, and the bus controller
refrains from starting prefetches that would be discarded due to the change of flow.
5.7.1.4 INSTRUCTION EXECUTION OVERLAP. Overlap is the time, measured in clock
cycles, that an instruction executes concurrently with the previous instruction. As shown in
Figure 5-31, portions of instructions A and B execute simultaneously, reducing total
execution time. Because portions of instructions B and C also overlap, overall execution
time for all three instructions is also reduced.
Each instruction contributes to the total overlap time. The portion of execution time at the
end of instruction A that can overlap the beginning of instruction B is called the tail of
instruction A. The portion of execution time at the beginning of instruction B that can
overlap the end of instruction A is called the head of instruction B. The total overlap time
between instructions A and B is the smaller tail of A and the head of B.
INSTRUCTION A
INSTRUCTION B
INSTRUCTION C
OVERLAP
OVERLAP
Figure 5-31. Simultaneous Instruction Execution
MOTOROLA
MC68340 USER’S MANUAL
5- 91
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