MC68340AG16VE Freescale Semiconductor, MC68340AG16VE Datasheet - Page 281

• Manufacturer Part Number: MC68340AG16VE
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16VE

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

IRQ—Interrupt Request
DONE—DMA Done
BES—Bus Error on Source
BED—Bus Error on Destination
CONF—Configuration Error
BRKP—Breakpoint
Bits 1, 0—Reserved
MOTOROLA
This bit is the logical OR of the DONE, BES, BED, CONF, and BRKP bits and is cleared
when they are all cleared. IRQ is positioned to allow conditional testing as a signed
binary integer. The state of this bit is not affected by the interrupt enable bits in the
CCR. The STR bit in the CCR cannot be set when this bit is set; all error status bits,
except the BRKP bit, must be cleared before the STR bit can be set.
A configuration error results when either the SAR or the DAR contains an address that
does not match the port size specified in the CCR and the BTC register does not match
the larger port size or is zero.
1 = An interrupt condition has occurred.
0 = An interrupt condition has not occurred.
1 = The DMA channel has terminated normally.
0 = The DMA channel has not terminated normally. This bit is cleared by writing a
1 = The DMA channel has terminated with a bus error during the read bus cycle.
0 = The DMA channel has not terminated with a bus error during the read bus cycle.
1 = The DMA channel has terminated with a bus error during the write bus cycle.
0 = The DMA channel has not terminated with a bus error during the write bus cycle.
1 = The CCR STR bit is set, and a configuration error is present.
0 = The CCR STR bit is set, and no configuration error exists. This bit is cleared by
1 = The breakpoint signal was set during a DMA transfer.
0 = The breakpoint signal was not set during a DMA transfer. This bit is cleared by
logic one or by a hardware reset. Writing a zero has no effect.
This bit is cleared by writing a logic one or by a hardware reset. Writing a zero
has no effect.
This bit is cleared by writing a logic one or by a hardware reset. Writing a zero
has no effect.
writing a logic one or by a hardware reset. Writing a zero has no effect.
writing a logic one or by a hardware reset. Writing a zero has no effect.
The CSR is cleared by writing $7C to its location. The DMA
channel cannot be started until the CSR DONE, BES, BED,
CONF and BRKP bits are cleared.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68340 USER’S MANUAL
Go to: www.freescale.com
NOTE
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