MC68340AG16VE Freescale Semiconductor, MC68340AG16VE Datasheet - Page 128

• Manufacturer Part Number: MC68340AG16VE
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16VE

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

NCS—No CPU Space
V—Valid Bit
4.3.4.2 ADDRESS MASK REGISTERS. There are four 32-bit address mask registers in
the chip select function, one for each chip select signal.
Address Mask 1
Address Mask 2
U = Unaffected by reset
AM31–AM8—Address Mask Bits 31–8
MOTOROLA
RESET:
RESET:
AM31
AM15
31
15
This bit specifies whether or not a chip select will assert on a CPU space access cycle
(FC3–FC0 = $7 or $F). If both supervisor data and program accesses are desired, while
ignoring CPU space accesses, then this bit should be set. The NCS bit is cleared at
reset.
This bit indicates that the contents of its base address register and address mask
register pair are valid. The programmed chip selects do not assert until the V-bit is set.
A reset clears the V-bit in each base address register, but does not change any other
bits in the base address and address mask registers ( CS0 is a special case, see 4.2.4.2
Global Chip Select Operation).
U
U
The address mask field, the upper 24 bits of each address mask register, defines the
chip select block size. The block size is equal to 2
the address mask field) + 8.
Any set bit masks the corresponding base address register bit (the base address
register bit becomes a don’t care). By masking the address bits independently, external
devices of different size address ranges can be used. Address mask bits can be set or
cleared in any order in the field, allowing a resource to reside in more than one area of
the address map. This field can be read or written at any time.
1 = Suppress the chip select on a CPU space access.
0 = Assert the chip select on a CPU space access.
1 = Contents are valid.
0 = Contents are not valid.
AM30
AM14
30
14
U
U
AM29
AM13
29
13
U
U
AM28
AM12
28
12
U
U
AM27
AM11
Freescale Semiconductor, Inc.
27
11
U
U
For More Information On This Product,
AM26
AM10
26
10
U
U
MC68340 USER’S MANUAL
Go to: www.freescale.com
AM25
AM9
25
U
U
9
AM24
AM8
24
U
U
8
AM23
FCM3
23
U
U
7
AM22
FCM2
22
U
U
6
n
, where n = (number of bits set in
AM21
FCM1
21
U
U
5
AM20
FCM0
20
U
U
4
$042, $04A, $052, $05A
$040, $048, $050, $058
AM19
DD1
19
U
U
3
Supervisor Only
Supervisor Only
AM18
DD0
18
U
U
2
AM17
PS1
17
U
U
1
AM16
PS0
4- 31
16
U
U
0