MC68340AG16VE Freescale Semiconductor, MC68340AG16VE Datasheet - Page 286

• Manufacturer Part Number: MC68340AG16VE
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16VE

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

For normal transfers aligned with the size and address, only two bus cycles are required
for each transfer: a read from the source and a write to the destination.
6.9 DMA CHANNEL INITIALIZATION SEQUENCE
The following paragraphs describe DMA channel initialization and operation. If the DMA
capability of the MC68340 is being used, the initialization steps should be performed
during the part initialization sequence. The mode operation steps should be performed to
start a DMA transfer. The DONE pin requires an external pullup resistor even if operating
only in the internal request mode.
6.9.1 DMA Channel Configuration
The following steps can be accomplished in any order when initializing the DMA channel.
These steps need to be performed for each channel used.
Module Configuration Register (MCR)
Interrupt Register (INTR)
Channel Control Register (CCR)
6-36
• Clear the stop bit (STP) for normal operation. (Only one STP bit exists for both
• Select whether to respond to or ignore FREEZE (FRZx bits). (Only one set of FRZx
• If desired, enable the external data bus operation in single-address mode (SE bit).
• Program the interrupt service mask to set the level below which interrupts are ignored
• Select the access privilege for the supervisor/user registers (SUPV bit).
• Program the master arbitration ID (MAID) to establish priority on the IMB between
• Select the interrupt arbitration level for the DMA channel (IARB bits). (Only one set of
• Program the interrupt priority level for the channel interrupt (INTL bits).
• Program the vector number for the channel interrupt (INTV bits).
• If desired, enable the interrupt when breakpoint is recognized and the channel is the
• If desired, enable the interrupt when done without an error condition (INTN bit).
• If desired, enable the interrupt when the channel encounters an error (INTE bit).
channels.)
bits exits for both channels.)
during a DMA transfer (ISM bits). The channel will begin operation when the level of
the CPU32 SR I2-I0 bits is less than or equal to the level of the DMA ISM bits.
both DMA channels. Note that the two DMA channels should have distinct MAIDs if
both channels are being used. (If they are programmed the same, channel 1 has
priority.)
IARB bits exits for both channels.)
bus master (INTB bit).
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68340 USER’S MANUAL
Go to: www.freescale.com
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