MC68340AG16VE Freescale Semiconductor, MC68340AG16VE Datasheet - Page 275

• Manufacturer Part Number: MC68340AG16VE
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16VE

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

SE—Single-Address Enable
Bit 11—Reserved
ISM2–ISM0—Interrupt Service Mask
SUPV—Supervisor/User
MAID—Master Arbitration ID
IARB — Interrupt Arbitration ID
MOTOROLA
This bit is implemented for future MC683xx family compatibility.
In dual-address mode, the SE bit has no effect.
These bits contain the interrupt service mask level for the channel. When the interrupt
service level on the IMB is greater than the interrupt service mask level, the DMA
vacates the bus and negates BR until the interrupt service level is less than or equal to
the interrupt service mask level.
The value of this bit has no effect on registers permanently defined as supervisor-only
access.
These bits establish bus arbitration priority level among modules that have the capability
of becoming bus master. For the MC68340, the MAID bits are used to arbitrate between
DMA channel 1 and channel 2. If both channels are programmed with the same MAID
level, channel 1 will have priority. These bits are implemented for future MC683xx
Family compatibility. In the MC68340, only the SIM and the DMA can be bus masters.
However, future versions of the MC683xx Family may incorporate other modules that
may also be bus masters. For these devices, the MAID bits will be required. For the
MAID bits, zero is the lowest priority and seven is the highest priority.
Each module that generates interrupts has an IARB field. These bits are used to
arbitrate for the bus in the case that two or more modules simultaneously generate an
interrupt at the same priority level. No two modules can share the same IARB value.
1 = In single-address mode, the external data bus is driven during a DMA transfer.
0 = In single-address mode, the external data bus remains in a high-impedance state
1 = The DMA channel registers defined as supervisor/user reside in supervisor data
0 = The DMA channel registers defined as supervisor/user reside in user data space
during a DMA transfer (used for intermodule DMA).
space and are only accessible from supervisor programs.
and are accessible from either supervisor or user programs.
When the CPU32 status register (SR) interrupt priority mask
bits I2–I0 are at a higher level than the DMA ISM bits, the DMA
channel will not start. The channel will begin operation when
the level of the SR I2–I0 bits is less than or equal to the level of
the DMA ISM bits.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68340 USER’S MANUAL
Go to: www.freescale.com
NOTE
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