IDT79RC32H434-400BCG IDT, Integrated Device Technology Inc, IDT79RC32H434-400BCG Datasheet - Page 8

• Manufacturer Part Number: IDT79RC32H434-400BCG
• Description: IC MPU 32BIT CORE 400MHZ 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Interprise™r

Specifications of IDT79RC32H434-400BCG

• Processor Type: MIPS32 32-Bit
• Speed: 400MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 79RC32H434-400BCG

IDT RC32434
SDI
SDO
I
SCL
SDA
Ethernet Interfaces
MIICL
MIICRS
MIIRXCLK
MIIRXD[3:0]
MIIRXDV
MIIRXER
MIITXCLK
MIITXD[3:0]
MIITXENP
MIITXER
MIIMDC
MIIMDIO
EJTAG / JTAG
JTAG_TMS
2
C Bus Interface
Signal
Type
I/O
I/O
I/O
I/O
I/O
O
O
O
O
I
I
I
I
I
I
I
I
Serial Data Input. This signal is used to shift in serial data. This pin may be
used as a bit input/output port.
Serial Data Output. This signal is used shift out serial data.
I
I
Ethernet MII Collision Detected. This signal is asserted by the ethernet PHY
when a collision is detected.
Ethernet MII Carrier Sense. This signal is asserted by the ethernet PHY when
either the transmit or receive medium is not idle.
Ethernet MII Receive Clock. This clock is a continuous clock that provides a
timing reference for the reception of data.
This pin also functions as the RMII REF_CLK input.
Ethernet MII Receive Data. This nibble wide data bus contains the data
received by the ethernet PHY.
This pin also functions as the RMII RXD[1:0] input.
Ethernet MII Receive Data Valid. The assertion of this signal indicates that
valid receive data is in the MII receive data bus.
This pin also functions as the RMII CRS_DV input.
Ethernet MII Receive Error. The assertion of this signal indicates that an error
was detected somewhere in the ethernet frame currently being sent in the MII
receive data bus.
This pin also functions as the RMII RX_ER input.
Ethernet MII Transmit Clock. This clock is a continuous clock that provides a
timing reference for the transfer of transmit data.
Ethernet MII Transmit Data. This nibble wide data bus contains the data to be
transmitted.
This pin also functions as the RMII TXD[1:0] output.
Ethernet MII Transmit Enable. The assertion of this signal indicates that data
is present on the MII for transmission.
This pin also functions as the RMII TX_EN output.
Ethernet MII Transmit Coding Error. When this signal is asserted together
with MIITXENP, the ethernet PHY will transmit symbols which are not valid data
or delimiters.
MII Management Data Clock. This signal is used as a timing reference for
transmission of data on the management interface.
MII Management Data. This bidirectional signal is used to transfer data
between the station management entity and the ethernet PHY.
JTAG Mode. The value on this signal controls the test mode select of the
boundary scan logic or JTAG Controller. When using the EJTAG debug inter-
face, this pin should be left disconnected (since there is an internal pull-up) or
driven high.
2
2
C Clock. I
C Data Bus. I
Table 1 Pin Description (Part 5 of 6)
2
C-bus clock.
2
C-bus data bus.
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Name/Description
January 19, 2006