IDT79RC32H434-400BCG IDT, Integrated Device Technology Inc, IDT79RC32H434-400BCG Datasheet - Page 19

• Manufacturer Part Number: IDT79RC32H434-400BCG
• Description: IC MPU 32BIT CORE 400MHZ 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Interprise™r

Specifications of IDT79RC32H434-400BCG

• Processor Type: MIPS32 32-Bit
• Speed: 400MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 79RC32H434-400BCG

IDT RC32434
Memory Bus - DDR Access
DDRDATA[15:0]
DDRDM[1:0]
DDRDQS[1:0]
DDRADDR[13:0],
DDRBA[1:0],
DDRCASN,
DDRCKE,
DDRCSN,
DDRRASN,
DDRWEN
1.
2.
Setup times are calculated as applicable clock period - Tdo max. For example, if the DDR is running at 266MHz, it uses a 133MHz input clock. The period for a 133MHz clock
Meets DDR timing requirements for 150MHz clock rate DDR SDRAMs with 300 ps remaining margin to compensate for PCB propagation mismatches, which is adequate to
guarantee functional timing, provided the RC32434 DDR layout guidelines are adhered to.
is 7.5ns. If the Tdo max value is 4.6ns, the T
propagation. Calculations for T
a 133MHz input clock is only 3.75ns. So, if the max Tdo is 1.9ns, we have 3.75ns minus 1.9ns = 1.85ns for T
this leaves 1.35ns slack for board propagation delays.
Signal
Symbol
Tskew_7g
Mem Control Signals
Tdo_7k
Tdo_7m
Tdo_7l
Tdo_7i
1.
2.
3.
4.
5.
6.
Warm reset condition caused by assertion of RSTN by an external agent.
The RC32434 tri-states the data bus, MDATA[7:0], negates all memory control signals, and itself asserts RSTN. The RC32434 continues to
drive the address bus throughout the entire warm reset.
The RC32434 negates RSTN after 4000 master clock (CLK) clock cycles.
External logic negates RSTN.
The RC32434 samples RSTN negated at least 4000 master clock (CLK) clock cycles after step 3 and starts driving the data bus,
MDATA[7:0].
CPU begins executing by taking a MIPS soft reset exception. The assertion of CSN[0] will occur no sooner than 16 clock cycles after the
RC32434 samples RSTN negated (i.e., step 5).
COLDRSTN
MDATA[7:0]
2
DS
RSTN
Reference
are similar, but since this parameter is taken relative to the DDRDQS signals, which are referenced on both edges, the effective period with
CLK
DDRDQSx
DDRDQSx
DDRCKP
DDRCKP
Edge
IS
Active
parameter is 7.5ns minus 4.6ns = 2.9ns. The DDR spec for this parameter is 1ns, so there is 1.9ns of slack left over for board
Figure 5 Externally Initiated Warm Reset AC Timing Waveform
1
-0.75
Min
1.2
1.2
1.0
266MHz
0
Table 7 DDR SDRAM Timing Characteristics
2
clock Cycles
4000 CLK
Max
0.75
0.9
1.9
1.9
4.0
3
-0.75
Min
1.0
1.0
1.0
19 of 53
300MHz
0
clock Cycles
4000 CLK
Max
0.75
0.8
1.7
1.7
4.3
4
Deasserted
1
5
Min
-0.7
0.7
0.7
1.0
350MHz
0
DS
. The DDR data sheet specs a value of 0.5ns for 266MHz, so
Max
FFFF_FFFF
0.7
1.5
1.5
0.7
4.0
Min
-0.7
0.0
0.5
0.5
1.0
400MHz
6
Max
0.6
1.4
1.4
0.7
4.0
Active
Unit
ns
ns
ns
ns
ns
January 19, 2006
See Figures 6
and 7.
Reference
Diagram
Timing