CY8CTMG201-48LTXI Cypress Semiconductor Corp, CY8CTMG201-48LTXI Datasheet - Page 60

• Manufacturer Part Number: CY8CTMG201-48LTXI
• Description: IC MCU 16K FLASH PSOC 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG201-48LTXI

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (16 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2972

6.2.3
The Port Drive Mode Bit Registers (PRTxDM0 and
PRTxDM1) specify the Drive mode for GPIO pins.
Bits 7 to 0: Drive Mode x[7:0]. In the PRTxDMx registers
there are four possible drive modes for each port pin. Two
mode bits are required to select one of these modes, and
these two bits are spread into two different registers
(PRTxDM0 and PRTxDM1). The bit position of the affected
port pin (for example, Pin[2] in Port 0) is the same as the bit
position of each of the two drive mode register bits that con-
trol the Drive mode for that pin (for example, bit[2] in
PRT0DM0 and bit[2] in PRT0DM1). The two bits from the
two registers are treated as a group. These are referred to
as DM1 and DM0, or together as DM[1:0]. Drive modes are
shown in
For analog I/O, set the drive mode to the High Z analog
mode, 10b. The 10b mode disables the block’s digital input
buffer so no crowbar current flows, even when the analog
input is not close to either power rail. If the 10b drive mode is
used, the pin is always read as a zero by the CPU and the
pin cannot generate a useful interrupt. (It is not strictly
required that you select High Z mode for analog operation.)
General Purpose I/O (GPIO)
60
1,xxh
1,xxh
LEGEND
xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers,
Address
refer to the
Table
PRTxDM0
PRTxDM1
Core Register Summary on page
PRTxDMx Registers
Name
6-3.
Bit 7
Bit 6
24.
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Bit 5
Bit 4
Drive Mode 0[7:0]
Drive Mode 1[7:0]
When digital inputs are needed on the same pin as analog
inputs, use the 11b Drive mode with the corresponding data
bit (in the PRTxDR register) set high.
The GPIO provides a default drive mode of high impedance,
analog (High Z). This is achieved by forcing the reset state
of all PRTxDM1 registers to FFh.
For additional information, refer to the
page
DM1
0
0
1
1
Modes
Drive
259, and the
DM0
Bit 3
0
1
0
1
Resistive pull up
Strong drive
High impedance,
analog ( reset state )
Open drain low
Pin State
Bit 2
PRTxDM1 register on page
Bit 1
Resistive high, strong low
Strong high, strong low
High Z high and low, digital input dis-
abled (for zero power) ( reset state )
High Z high (digital input enabled),
strong low.
PRTxDM0 register on
Description
Bit 0
260.
RW : FF
Access
RW : 00
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