CY8CTMG201-48LTXI Cypress Semiconductor Corp, CY8CTMG201-48LTXI Datasheet - Page 192

• Manufacturer Part Number: CY8CTMG201-48LTXI
• Description: IC MCU 16K FLASH PSOC 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG201-48LTXI

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (16 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2972

SPI_CR
21.3.5
Individual Register Names and Addresses:
SPI_CR : 0,2Bh
This register is the SPI control register.
The LSb First, Clock Phase, and Clock Polarity bits are configuration bits. Do not change them once the block is enabled.
These bits can be set at the same time that the block is enabled. For additional information, refer to the
on page 147
Bit
7
6
5
4
3
2
1
0
192
Access : POR
Bit Name
0,2Bh
LSb First
Overrun
SPI Complete
TX Reg Empty
RX Reg Full
Clock Phase
Clock Polarity
Enable
Name
in the SPI chapter.
SPI_CR
SPI Control Register
LSb First
RW : 0
7
Overrun
R : 0
6
Description
Do not change this bit during an SPI transfer.
0
1
0
1
0
1
Reset state and the state when the block is disabled is ‘1’.
0
1
0
1
0
1
0
1
0
1
SPI Complete
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Data is shifted out MSb first.
Data is shifted out LSb first.
No overrun has occurred.
Overrun has occurred. Indicates that a new byte is received and loaded into the RX Buffer
before the previous one is read. It is cleared on a read of this (CR0) register.
Indicates that a byte may still be in the process of shifting out, or no transmission is active.
Indicates that a byte is shifted out and all associated clocks are generated. It is cleared on a
read of this (CR0) register. Optional interrupt.
Indicates that a byte is currently buffered in the TX register.
Indicates that a byte is written to the TX register and cleared on write of the TX Buffer (DR1)
register. This is the default interrupt. This status is initially asserted on block enable; how-
ever, the TX Reg Empty interrupt occurs only after the first data byte is written and trans-
ferred into the shifter.
RX register is empty.
A byte is received and loaded into the RX register. It is cleared on a read of the RX Buffer
(DR2) register.
Data is latched on the leading clock edge. Data changes on the trailing edge (modes 0, 1).
Data changes on the leading clock edge. Data is latched on the trailing edge (modes 2, 3).
Non-inverted, clock idles low (modes 0, 2).
Inverted, clock idles high (modes 1, 3).
SPI function is not enabled.
SPI function is enabled.
R : 0
5
TX Reg Empty
R : 1
4
RX Reg Full
R : 0
3
Clock Phase
RW : 0
2
Clock Polarity
RW : 0
1
Register Definitions
0,2Bh
Enable
RW : 0
0
[+] Feedback