CY8CTMG201-48LTXI Cypress Semiconductor Corp, CY8CTMG201-48LTXI Datasheet - Page 57

• Manufacturer Part Number: CY8CTMG201-48LTXI
• Description: IC MCU 16K FLASH PSOC 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTMG201-48LTXI

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (16 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2972

be greater than 2.7V, and for 1.8V output level, chip Vdd
should be greater than 2.5V.
6.1.5
Port 0 has a stronger high drive. However, unlike Port 1, it
does not have an option for regulating the outputs when in
strong drive mode. Refer to the device data sheet for the dif-
ferent current sourcing specifications of Port 0.
6.1.6
You have the ability to individually configure each GPIO pin
for interrupt capability. Pins are configured by pin interrupt
enables and also by a chip wide selection for interrupt state
with this global selection. Pins can be set to interrupt when
the pin is low or when it changes from the last time it was
read. The block provides an open drain interrupt output
(INTO) that is connected to other GPIO blocks in a wire-OR
fashion.
All pin interrupts that are wire-OR’ed together are tied to the
same system GPIO interrupt. Therefore, if interrupts are
enabled on multiple pins, the user’s interrupt service routine
must provide a mechanism to determine which pin was the
source of the interrupt.
Using a GPIO interrupt requires these steps:
1. Set the Interrupt mode (IOINT bit in the IO_CFG1 regis-
2. Enable the bit interrupt in the GPIO block.
3. Set the mask bit for the (global) GPIO interrupt.
4. Assert the overall Global Interrupt Enable.
The first step sets a common interrupt mode for all pins.
The second step, bit interrupt enable, is set at the GPIO pin
level (that is, at each port pin), by way of the PRTxIE regis-
ters.
The last two steps are common to all interrupts and
described in the
At the GPIO block level, asserting the INTO line depends
only on the bit interrupt enable and the state of the pin rela-
tive to the chosen Interrupt mode. At the PSoC device level,
due to their wire-OR nature, the GPIO interrupts are neither
true edge sensitive interrupts nor true level sensitive inter-
rupts. They are considered edge sensitive for asserting, but
level sensitive for release of the wire-OR interrupt line.
If no GPIO interrupts are asserting, a GPIO interrupt occurs
whenever a GPIO pin interrupt enable is set and the GPIO
pin transitions (if not already transitioned) appropriately high
or low to match the interrupt mode configuration. After this
happens, the INTO line pulls low to assert the GPIO inter-
rupt. This assumes the other system level enables are on,
such as setting the global GPIO interrupt enable and the
Global Interrupt Enable. Setting the pin interrupt enable may
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
ter).
Port 0 Distinctions
GPIO Block Interrupts
Interrupt Controller chapter on page
45.
immediately assert INTO, if the Interrupt mode conditions
are already being met at the pin.
After INTO pulls low, it continues to hold INTO low until one
of these conditions change:
■
■
■
■
After one of these conditions is met, the INTO releases. At
this point, another GPIO pin (or this pin again) could assert
its INTO pin, pulling the common line low to assert a new
interrupt.
Note the following behavior from this level release feature. If
one pin is asserting INTO and then a second pin asserts its
INTO, when the first pin releases its INTO, the second pin is
already driving INTO and thus no change is seen (that is, no
new interrupt is asserted on the GPIO interrupt). Take care,
using polling or the states of the GPIO pin and Global Inter-
rupt Enables, to catch all interrupts among a set of wire-OR
GPIO blocks.
Figure 6-2. GPIO Interrupt Logic Diagram
6.1.6.1
GPIO interrupts use the IOINT bit from the IO_CFG1 regis-
ter. The setting of IOINT determines the interrupt mode for
all GPIO.
Interrupt mode IOINT=0 means that the block asserts the
GPIO interrupt line (INTO) when the pin voltage is low, if the
block’s bit interrupt enable line is set (high).
Interrupt mode IOINT=1 means that the block asserts the
interrupt line (INTO) when the pin voltage is the opposite of
the last state read from the pin, if the block’s bit interrupt
enable line is set high. This mode switches between low
mode and high mode, depending upon the last value read
from the port during reads of the data register (PRTxDR). If
the last value read from the GPIO was 0, the GPIO pin is in
Port
Read
IE (PRTxIE.n)
INBUF (from GPIO Block Diagram)
The pin interrupt enable is cleared.
The voltage at pin transitions to the opposite state.
In interrupt-on-change mode, the GPIO data register is
read thus setting the local interrupt level to the opposite
state.
The Interrupt mode is changed so that the current pin
state does not create an interrupt.
D
Q
Interrupt Modes
IOINT
General Purpose I/O (GPIO)
Interrupt Mode
IE
0
0
1
1
IOINT
0
1
0
1
Interrupt
Disabled
Disabled
Low
Change from last read
INTO
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