CY7C66113C-LFXC Cypress Semiconductor Corp, CY7C66113C-LFXC Datasheet - Page 41
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CY7C66113C-LFXC
Manufacturer Part Number
CY7C66113C-LFXC
Description
IC MCU 8K USB HUB 4 PORT 56VQFN
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY7C66013C-PVXC.pdf
(59 pages)
Specifications of CY7C66113C-LFXC
Applications
USB Hub/Microcontroller
Core Processor
M8
Program Memory Type
OTP (8 kB)
Controller Series
USB Hub
Ram Size
256 x 8
Interface
I²C, USB, HAPI
Number Of I /o
31
Voltage - Supply
4 V ~ 5.25 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
Controller Family/series
(8051) USB
Ram Memory Size
256Byte
No. Of Timers
1
Digital Ic Case Style
QFN
Operating Temperature Range
0°C To +70°C
No. Of Pins
56
Core Size
8 Bit
Embedded Interface Type
HAPI, I2C, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C66113C-LFXC
Manufacturer:
CYPRESS
Quantity:
250
Part Number:
CY7C66113C-LFXC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Endpoint Mode and Count Registers Update and
Locking Mechanism
The contents of the endpoint mode and counter registers are
updated, based on the packet flow diagram in
time points, UPDATE and SETUP, are shown in the same figure.
The following activities occur at each time point:
SETUP:
The SETUP bit of the endpoint 0 mode register is forced HIGH
at this time. This bit is forced HIGH by the SIE until the end of the
data phase of a control write transfer. The SETUP bit can not be
cleared by firmware during this time.
The affected mode and counter registers of endpoint 0 are
locked from any CPU writes when they are updated. These
registers are unlocked by a CPU read, only if the read operation
occurs after the UPDATE. The firmware needs to perform a
register read as a part of the endpoint ISR processing to unlock
Document Number: 38-08024 Rev. *D
Figure
47. Two
the effected registers. The locking mechanism on mode and
counter registers ensures that the firmware recognizes the
changes that the SIE might have made since the previous I/O
read of that register.
UPDATE:
1. Endpoint Mode Register – All the bits are updated (except the
2. Counter Registers – All bits are updated.
3. Interrupt – If an interrupt is to be generated as a result of the
4. The contents of the updated endpoint 0 mode and counter
SETUP bit of the endpoint 0 mode register).
transaction, the interrupt flag for the corresponding endpoint
is set at this time. For details on what conditions are required
to generate an endpoint interrupt, refer to
registers are locked, except the SETUP bit of the endpoint 0
mode register which was locked earlier.
CY7C66013C, CY7C66113C
Table
Page 41 of 59
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