CY7C66113C-LFXC Cypress Semiconductor Corp, CY7C66113C-LFXC Datasheet - Page 29

• Manufacturer Part Number: CY7C66113C-LFXC
• Description: IC MCU 8K USB HUB 4 PORT 56VQFN
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C66113C-LFXC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 31
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Controller Family/series: (8051) USB
• Ram Memory Size: 256Byte
• No. Of Timers: 1
• Digital Ic Case Style: QFN
• Operating Temperature Range: 0°C To +70°C
• No. Of Pins: 56
• Core Size: 8 Bit
• Embedded Interface Type: HAPI, I2C, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Although Reset is not an interrupt, the first instruction executed after a reset is at PROM address 0x0000h—which corresponds to the
first entry in the Interrupt Vector Table. Because the JMP instruction is two bytes long, the interrupt vectors occupy two bytes.
Table 11. Interrupt Vector Assignments
Interrupt Latency
Interrupt latency is calculated from the following equation:
Interrupt latency =
current instruction) + (10 clock cycles for the CALL instruction) +
For example, if a five clock cycle instruction such as JC is being
executed when an interrupt occurs, the first instruction of the
Interrupt Service Routine executes a minimum of 16 clocks
(1+10+5) or a maximum of 20 clocks (5+10+5) after the interrupt
is issued. For a 12 MHz internal clock (6 MHz crystal), 20 clock
periods is 20/12 MHz = 1.667 μs.
USB Bus Reset Interrupt
The USB Controller recognizes a USB Reset when a Single
Ended Zero (SE0) condition persists on the upstream USB port
for 12–16 μs. SE0 is defined as the condition in which both the
D+ line and the D– line are LOW. A USB Bus Reset may be
recognized for an SE0 as short as 12 μs, but is always
recognized for an SE0 longer than 16 μs. When a USB Bus
Reset is detected, bit 5 of the Processor Status and Control
Register
controller clears the following registers:
Document Number: 38-08024 Rev. *D
Not Applicable
1
2
3
4
5
6
7
8
9
10
11
12
SIE Section:
Hub Section:
Interrupt Vector Number
(Figure
28) is set to record this event. In addition, the
USB Device Address Registers (0x10,
0x40)
Hub Ports Connect Status (0x48)
Hub Ports Enable (0x49)
Hub Ports Speed (0x4A)
Hub Ports Suspend (0x4D)
Hub Ports Resume Status (0x4E)
Hub Ports SE0 Status (0x4F)
Hub Ports Data (0x50)
Hub Downstream Force (0x51).
(Number of clock cycles remaining in the
(5 clock cycles for the JMP instruction).
0x0000
0x0002
0x0004
0x0006
0x0008
0x000A
0x000C
0x000E
0x0010
0x0012
0x0014
0x0016
0x0018
ROM Address
A USB Bus Reset Interrupt is generated at the end of the USB
Bus Reset condition when the SE0 state is deasserted. If the
USB reset occurs during the start up delay following a POR, the
delay is aborted as described in
Timer Interrupt
There are two periodic timer interrupts: the 128 μs interrupt and
the 1.024 ms interrupt. The user should disable both timer
interrupts before going into the suspend mode to avoid possible
conflicts between servicing the timer interrupts first or the
suspend request first.
USB Endpoint Interrupts
There are five USB endpoint interrupts, one per endpoint. A USB
endpoint interrupt is generated after the USB host writes to a
USB endpoint FIFO or after the USB controller sends a packet
to the USB host. The interrupt is generated on the last packet of
the transaction. For example, on the host’s ACK during an IN, or
on the device ACK during on OUT. If no ACK is received during
an IN transaction, no interrupt is generated.
USB Hub Interrupt
A USB hub interrupt is generated by the hardware after a
connect/disconnect change, babble, or a resume event is
detected by the USB repeater hardware. The babble and resume
events are additionally gated by the corresponding bits of the
Hub Port Enable Register
disconnect event on a port does not generate an interrupt if the
SIE does not drive the port (that is, the port is being forced).
Execution after Reset begins here
USB Bus Reset interrupt
128 μs timer interrupt
1.024 ms timer interrupt
USB Address A Endpoint 0 interrupt
USB Address A Endpoint 1 interrupt
USB Address A Endpoint 2 interrupt
USB Address B Endpoint 0 interrupt
USB Address B Endpoint 1 interrupt
USB Hub interrupt
DAC interrupt
GPIO and HAPI interrupt
I
2
C interrupt
CY7C66013C, CY7C66113C
Function
(Figure
Power on Reset
35). The connect and
on page 14.
Page 29 of 59
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