CY7C66113C-LFXC Cypress Semiconductor Corp, CY7C66113C-LFXC Datasheet - Page 20

• Manufacturer Part Number: CY7C66113C-LFXC
• Description: IC MCU 8K USB HUB 4 PORT 56VQFN
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C66113C-LFXC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 31
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Controller Family/series: (8051) USB
• Ram Memory Size: 256Byte
• No. Of Timers: 1
• Digital Ic Case Style: QFN
• Operating Temperature Range: 0°C To +70°C
• No. Of Pins: 56
• Core Size: 8 Bit
• Embedded Interface Type: HAPI, I2C, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

DAC Isink Registers
Each DAC I/O pin has an associated DAC Isink register to program the output sink current when the output is driven LOW. The first
Isink register (0x38) controls the current for DAC[0], the second (0x39) for DAC[1], and so on until the Isink register at 0x3F, controls
the current to DAC[7].
DAC Sink Register
Bit [3..0]: Isink [x] (x= 0..3)
Writing all ‘0’s to the Isink register causes 1/5 of the max current
to flow through the DAC I/O pin. Writing all ‘1’s to the Isink
register provides the maximum current flow through the pin. The
DAC Port Interrupts
A DAC port interrupt is enabled or disabled for each pin individually. The DAC Port Interrupt Enable register provides this feature with
an interrupt enable bit for each DAC I/O pin. All of the DAC Port Interrupt Enable register bits are cleared to ‘0’ during a reset. All DAC
pins share a common interrupt, as explained in
DAC Port Interrupt
Bit [7..0]: Enable bit x (x= 0..7)
As an additional benefit, the interrupt polarity for each DAC pin
is programmable with the DAC Port Interrupt Polarity register.
Writing a ‘0’ to a bit selects negative polarity (falling edge) that
DAC I/O Interrupt Polarity
Bit [7..0]: Polarity bit x (x= 0..7)
Document Number: 38-08024 Rev. *D
Bit #
Bit Name
Read/Write
Reset
Bit #
Bit Name
Read/Write
Reset
Bit #
Bit Name
Read/Write
Reset
1 = Enables interrupts from the corresponding bit position; 0=
Disables interrupts from the corresponding bit position
1= Selects positive polarity (rising edge) that causes an
interrupt (if enabled); 0 = Selects negative polarity (falling
edge) that causes an interrupt (if enabled).
7
Reserved
-
7
Enable Bit 7 Enable Bit 6 Enable Bit 5 Enable Bit 4 Enable Bit 3 Enable Bit 2 Enable Bit 1 Enable Bit 0
W
0
7
Polarity Bit 7 Polarity Bit 6 Polarity Bit 5 Polarity Bit 4 Polarity Bit 3 Polarity Bit 2 Polarity Bit 1 Polarity Bit 0
W
0
6
Reserved
-
6
W
0
6
W
0
5
Reserved
-
5
W
0
5
W
0
Figure 21. DAC Port Interrupt Polarity
Figure 20. DAC Port Interrupt Enable
DAC Interrupt
Figure 19. DAC Sink Register
4
W
0
4
Reserved
-
4
W
0
on page 30.
other 14 states of the DAC sink current are evenly spaced
between these two values.
Bit [7..4]: Reserved
causes an interrupt (if enabled) if a falling edge transition occurs
on the corresponding input pin. Writing a ‘1’ to a bit in this register
selects positive polarity (rising edge) that causes an interrupt (if
enabled) if a rising edge transition occurs on the corresponding
input pin. All of the DAC Port Interrupt Polarity register bits are
cleared during a reset.
3
Isink[3]
W
0
3
W
0
3
W
0
CY7C66013C, CY7C66113C
2
W
0
2
Isink[2]
W
0
2
W
0
1
W
0
1
Isink[1]
W
0
1
W
0
ADDRESS 0x38 –0x3F
ADDRESS 0x31
ADDRESS 0x32
Isink[0]
0
W
0
0
W
0
0
W
0
Page 20 of 59
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