CY7C66113C-LFXC Cypress Semiconductor Corp, CY7C66113C-LFXC Datasheet - Page 28

• Manufacturer Part Number: CY7C66113C-LFXC
• Description: IC MCU 8K USB HUB 4 PORT 56VQFN
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C66113C-LFXC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 31
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Controller Family/series: (8051) USB
• Ram Memory Size: 256Byte
• No. Of Timers: 1
• Digital Ic Case Style: QFN
• Operating Temperature Range: 0°C To +70°C
• No. Of Pins: 56
• Core Size: 8 Bit
• Embedded Interface Type: HAPI, I2C, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

is serviced following the completion of the currently executing
instruction.
When servicing an interrupt, the hardware does the following:
The instruction in the interrupt table is typically a JMP instruction
to the address of the Interrupt Service Routine (ISR). The user
re-enables interrupts in the interrupt service routine by executing
an EI instruction. Interrupts are nested to a level limited only by
the available stack space.
The Program Counter value and the Carry and Zero flags (CF,
ZF) are stored onto the Program Stack by the automatic CALL
instruction generated as part of the interrupt acknowledge
process. The user firmware is responsible for ensuring that the
processor state is preserved and restored during an interrupt.
Document Number: 38-08024 Rev. *D
1. Disables all interrupts by clearing the Global Interrupt Enable
2. Clears the flip flop of the current interrupt.
3. Generates an automatic CALL instruction to the ROM
bit in the CPU (the state of this bit is read at Bit 2 of the
Processor Status and Control Register,
address associated with the interrupt being serviced (that is,
the Interrupt Vector).
AddrA ENP2 Int
USB Reset Int
I
2
C Int
1
1
1
CLK
D
D
CLK
CLK
D
CLR
CLR
CLR
Q
Q
Q
(Reg 0x21)
Enable [2]
(Reg 0x20)
(Reg 0x20)
Enable [0]
Enable [6]
Figure 31. Interrupt Controller Function Diagram
Figure
28).
USB Reset IRQ
AddrA EP0 IRQ
AddrA EP1 CLR
AddrA EP1 IRQ
AddrA EP2 CLR
AddrA EP2 IRQ
AddrB EP0 CLR
AddrB EP0 IRQ
AddrB EP1 CLR
AddrB EP1 IRQ
DAC IRQ
GPIO/HAPI IRQ
128-μs CLR
128-μs IRQ
1-ms CLR
1-ms IRQ
AddrA EP0 CLR
Hub CLR
Hub IRQ
DAC CLR
GPIO/HAPI CLR
I
USB Reset Clear Interrupt
I
2
Interrupt Priority Encoder
2
C CLR
C IRQ
The PUSH A instruction should typically be used as the first
command in the ISR to save the accumulator value and the POP
A instruction should be used to restore the accumulator value
just before the RETI instruction. The program counter CF and ZF
are restored and interrupts are enabled when the RETI
instruction is executed.
The DI and EI instructions are used to disable and enable
interrupts, respectively. These instructions affect only the Global
Interrupt Enable bit of the CPU. If desired, EI is used to re-enable
interrupts while inside an ISR, instead of waiting for the RETI that
exists the ISR. While the global interrupt enable bit is cleared,
the presence of a pending interrupt is detected by examining the
IRQ Sense bit (Bit 7 in the Processor Status and Control
Register).
Interrupt Vectors
The Interrupt Vectors supported by the USB Controller are listed
in
interrupt) has the highest priority, and the highest numbered
interrupt (I
Table
11. The lowest numbered interrupt (USB Bus Reset
2
C interrupt) has the lowest priority.
IRQout
Vector
CY7C66013C, CY7C66113C
Acknowledge
To CPU
CPU
Interrupt
Interrupt
Enable
Global
CLR
Bit
Controlled by DI, EI, and
RETI Instructions
IRQ Sense
Int Enable
Sense
Page 28 of 59
IRQ
[+] Feedback