CY7C66113C-LFXC Cypress Semiconductor Corp, CY7C66113C-LFXC Datasheet - Page 39

• Manufacturer Part Number: CY7C66113C-LFXC
• Description: IC MCU 8K USB HUB 4 PORT 56VQFN
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C66113C-LFXC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 31
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Controller Family/series: (8051) USB
• Ram Memory Size: 256Byte
• No. Of Timers: 1
• Digital Ic Case Style: QFN
• Operating Temperature Range: 0°C To +70°C
• No. Of Pins: 56
• Core Size: 8 Bit
• Embedded Interface Type: HAPI, I2C, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

USB Device Endpoint Zero Mode (A0, B0)
Bits[3..0]: Mode
These sets the mode which control how the control endpoint
responds to traffic.
Bit 4: ACK
This bit is set whenever the SIE engages in a transaction to the
register’s endpoint that completes with an ACK packet.
Bit 5: Endpoint 0 OUT Received
1 = Token received is an OUT token. 0 = Token received is not
an OUT token. This bit is set by the SIE to report the type of token
received by the corresponding device address is an OUT token.
The bit must be cleared by firmware as part of the USB
processing.
Bit 6: Endpoint 0 IN Received
1 = Token received is an IN token. 0 = Token received is not an
IN token. This bit is set by the SIE to report the type of token
received by the corresponding device address is an IN token.
The bit must be cleared by firmware as part of the USB
processing.
Bit 7: Endpoint 0 SETUP Received
1 = Token received is a SETUP token. 0 = Token received is not
a SETUP token. This bit is set ONLY by the SIE to report the type
of token received by the corresponding device address is a
SETUP token. Any write to this bit by the CPU clears it (set it to
0). The bit is forced HIGH from the start of the data packet phase
of the SETUP transaction until the start of the ACK packet
returned by the SIE. The CPU should not clear this bit during this
interval, and subsequently, until the CPU first does an IORD to
this endpoint 0 mode register. The bit must be cleared by
firmware as part of the USB processing.
Document Number: 38-08024 Rev. *D
Bit #
Bit Name
Read/Write
Reset
7
Endpoint 0
SETUP
Received
R/W
0
6
Endpoint 0 IN
Received
R/W
0
Figure 44. USB Endpoint 0 Mode Registers
5
Endpoint 0
OUT
Received
R/W
0
4
ACK
R/W
0
Note In 5-endpoint mode (USB Status And Control Register Bits
[7,6] are set to [0,1] or [1,1]), Register 0x42 serves as non control
endpoint 3, and has the format for non control endpoints shown
in
Bits[6:0] of the endpoint 0 mode register are locked from CPU
write operations whenever the SIE has updated one of these bits,
which the SIE does only at the end of the token phase of a
transaction (SETUP... Data... ACK, OUT... Data... ACK, or IN...
Data... ACK). The CPU unlocks these bits by doing a subsequent
read of this register. Only endpoint 0 mode registers are locked
when updated. The locking mechanism does not apply to the
mode registers of other endpoints.
Because of these hardware locking features, firmware must
perform an IORD after an IOWR to an endpoint 0 register. This
verifies that the contents have changed as desired, and that the
SIE has not updated these values.
While the SETUP bit is set, the CPU cannot write to the endpoint
zero FIFOs. This prevents firmware from overwriting an incoming
SETUP transaction before firmware has a chance to read the
SETUP data. Refer to
memory locations.
The Mode bits (bits [3:0]) control how the endpoint responds to
USB bus traffic. The mode bit encoding is shown in
Additional information on the mode bits are found in
Table
Note The SIE offers an “Ack out - Status in” mode and not an
“Ack out - Nak in” mode. Therefore, if following the status stage
of a Control Write transfer a USB host were to immediately start
the next transfer, the new Setup packet could override the data
payload of the data stage of the previous Control Write.
Figure
15.
3
Mode Bit 3
R/W
0
45.
CY7C66013C, CY7C66113C
2
Mode Bit 2
R/W
0
Table 14
ADDRESSES
for the appropriate endpoint zero
1
Mode Bit 1
R/W
0
0x12(A0) and 0x42(B0)
0
Mode Bit 0
R/W
0
Page 39 of 59
Table 16
Table
and
12.
[+] Feedback