XC5VLX30T-1FFG665CES Xilinx Inc, XC5VLX30T-1FFG665CES Datasheet - Page 36
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XC5VLX30T-1FFG665CES
Manufacturer Part Number
XC5VLX30T-1FFG665CES
Description
IC FPGA VIRTEX-5 ES 30K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30T-1FFG665CES
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Total Ram Bits
1327104
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Part Number:
XC5VLX30T-1FFG665CES
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Chapter 1: Clock Resources
36
Additional Use Models
Asynchronous Mux Using BUFGCTRL
In some cases an application requires immediate switching between clock inputs or
bypassing the edge sensitivity of BUFGCTRL. An example is when one of the clock inputs
is no longer switching. If this happens, the clock output would not have the proper
switching conditions because the BUFGCTRL never detected a clock edge. This case uses
the asynchronous mux.
design example.
X-Ref Target - Figure 1-13
X-Ref Target - Figure 1-14
In
•
•
•
•
Figure
The current clock is from I0.
S is activated High.
The Clock output immediately switches to I1.
When Ignore signals are asserted High, glitch protection is disabled.
Figure 1-13: Asynchronous Mux with BUFGCTRL Design Example
1-14:
I1
I0
O
S
I1
I0
Asynchronous MUX
S
Figure 1-14
Design Example
Figure 1-14: Asynchronous Mux Timing Diagram
at I0
Figure 1-13
www.xilinx.com
shows the asynchronous mux timing diagram.
T
BCCKO_O
O
illustrates an asynchronous mux with BUFGCTRL
S
Begin I1
V
V
V
V
DD
DD
DD
DD
IGNORE1
CE1
S1
I1
I0
S0
CE0
IGNORE0
T
BCCKO_O
ug190_1_13_032306
UG190_1_14_032306
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
O
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