XC5VLX30T-1FFG665CES Xilinx Inc, XC5VLX30T-1FFG665CES Datasheet - Page 112
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XC5VLX30T-1FFG665CES
Manufacturer Part Number
XC5VLX30T-1FFG665CES
Description
IC FPGA VIRTEX-5 ES 30K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30T-1FFG665CES
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Total Ram Bits
1327104
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Part Number:
XC5VLX30T-1FFG665CES
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Quantity:
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Chapter 3: Phase-Locked Loops (PLLs)
Table 3-9: PLL Attributes When in Virtex-4 FPGA PMCD Legacy Mode
Table 3-10: PLL Ports in Virtex-4 FPGA PMCD Legacy Mode
112
PLL_PMCD_MODE
EN_REL
RST_DEASSERT_CLK
Port Name
CLKOUT0
CLKOUT1
CLKOUT2
CLKOUT3
CLKOUT4
CLKFB
CLKIN
REL
RST
Attribute
Output
Output
Output
Output
Output
Input
Input
Input
Input
I/O
Table 3-8: Mapping of Port Names (Continued)
Table 3-9
Table 3-10
Boolean
Boolean
String
Type
Virtex-4 FPGA
Virtex-4 FPGA PMCD legacy mode CLKB input clock to the PMCD.
Virtex-4 FPGA PMCD legacy mode CLKA input clock to the PMCD.
RST is the reset input to the Virtex-4 FPGA PMCD legacy mode. Asserting RST signal
asynchronously forces all outputs Low. Deasserting RST synchronously allows all
outputs to toggle.
REL is the release input to the Virtex-4 FPGA PMCD legacy mode. Asserting the REL
signal releases the divided outputs synchronous to CLKA.
Virtex-4 FPGA PMCD legacy mode CLKB1.
Virtex-4 FPGA PMCD legacy mode CLKA1.
Virtex-4 FPGA PMCD legacy mode CLKA1D2.
Virtex-4 FPGA PMCD legacy mode CLKA1D4.
Virtex-4 FPGA PMCD legacy mode CLKA1D8.
Port Name
CLKC1
CLKD1
CLKB1
shows the PLL attributes in Virtex-4 FPGA PMCD legacy mode.
Allowed Values
TRUE or FALSE
TRUE or FALSE
shows the PLL ports in Virtex-4 FPGA PMCD legacy mode.
RST
REL
CLKA
CLKB
www.xilinx.com
Default
FALSE
FALSE
CLKA
Virtex-5 FPGA
CLKFBOUT
Port Name
REL
n/a
RST
n/a
Enables PLL to act as PMCDs
When in PMCD mode (PLL_PMCD_MODE = TRUE),
specifies release of divided clock CLKA outputs when
the REL input pin is asserted.
When in PMCD mode (PLL_PMCD_MODE = TRUE),
specifies a clock to synchronize with the release of
RST.
Pin Description
Description
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
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