XC5VLX30T-1FFG665CES Xilinx Inc, XC5VLX30T-1FFG665CES Datasheet - Page 179
![IC FPGA VIRTEX-5 ES 30K 665FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX30T-1FFG665CES
Manufacturer Part Number
XC5VLX30T-1FFG665CES
Description
IC FPGA VIRTEX-5 ES 30K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30T-1FFG665CES
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Total Ram Bits
1327104
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX30T-1FFG665CES
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Table 5-3: Truth Table when SRLOW is Used (Default Condition) (Continued)
Table 5-4: Truth Table when SRHIGH is Used
X-Ref Target - Figure 5-5
SRHIGH and SRLOW can be set individually for each storage element in a slice. The choice
of synchronous (SYNC) or asynchronous (ASYNC) set/reset (SRTYPE) cannot be set
individually for each storage element in a slice.
SR
SR
1
1
0
0
1
1
Figure 5-5: Register/Latch Configuration in a Slice
CLK
DX
CX
SR
BX
CE
AX
www.xilinx.com
LUT D Output
LUT C Output
LUT B Output
LUT A Output
REV
REV
0
1
0
1
0
1
D
CE
CK
D
CE
CK
D
CE
CK
D
CE
CK
SR
SR
SR
SR
DFF
CFF
BFF
AFF
FF
LATCH
INIT1
INIT0
SRHIGH
SRLOW
FF
LATCH
INIT1
INIT0
SRHIGH
SRLOW
FF
LATCH
INIT1
INIT0
SRHIGH
SRLOW
FF
LATCH
INIT1
INIT0
SRHIGH
SRLOW
REV
REV
REV
REV
Q
Q
Q
Q
UG190_5_05_071207
Reset Type
Sync
Async
No Logic Change
DQ
CQ
BQ
AQ
Function
Function
0
0
0
1
0
CLB Overview
179
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