XC5VLX30T-1FFG665CES Xilinx Inc, XC5VLX30T-1FFG665CES Datasheet - Page 135
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XC5VLX30T-1FFG665CES
Manufacturer Part Number
XC5VLX30T-1FFG665CES
Description
IC FPGA VIRTEX-5 ES 30K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30T-1FFG665CES
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Total Ram Bits
1327104
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Part Number:
XC5VLX30T-1FFG665CES
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Table 4-11: Block RAM Timing Parameters
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Setup and Hold Relative to Clock (CLK)
Notes:
1. While EN is active, ADDR inputs must be stable during the entire setup/hold time window, even if WE is inactive. Violating this
Clock to Out Delays
(register mode)
T
T
T
T
requirement can result in block RAM data corruption. If ADDR timing could violate the specified requirements, EN must be inactive
(disabled).
(latch mode)
Parameter
RCCK_REGCE
RCKC_REGCE
T
T
T
T
T
T
RCCK_ADDR
RCKC_ADDR
T
T
T
T
RCCK_SSR
RCKC_SSR
RCCK_WE
RCKC_WE
RCKO_DO
RCKO_DO
RCCK_EN
RCKC_EN
RDCK_DI
RCKD_DI
Block RAM Timing Parameters
T
RxCK_x
Optional Output
Clock to Output
Clock to Output
Register Enable
Address inputs
Synchronous
Write Enable
Data inputs
Function
Set/Reset
Table 4-11
Enable
= Setup time (before clock edge) and T
shows the Virtex-5 FPGA block RAM timing parameters.
Control
REGCE
CLK to
CLK to
Signal
ADDR
SSR
WE
DO
DO
EN
DI
Time before the clock that address signals must be stable at the
ADDR inputs of the block RAM.
Time after the clock that address signals must be stable at the ADDR
inputs of the block RAM.
Time before the clock that data must be stable at the DI inputs of the
block RAM.
Time after the clock that data must be stable at the DI inputs of the
block RAM.
Time before the clock that the enable signal must be stable at the EN
input of the block RAM.
Time after the clock that the enable signal must be stable at the EN
input of the block RAM.
Time before the clock that the synchronous set/reset signal must be
stable at the SSR input of the block RAM.
Time after the clock that the synchronous set/reset signal must be
stable at the SSR input of the block RAM.
Time before the clock that the write enable signal must be stable at
the WE input of the block RAM.
Time after the clock that the write enable signal must be stable at the
WE input of the block RAM.
Time before the CLK that the register enable signal must be stable at
the REGCE input of the block RAM.
Time after the clock that the register enable signal must be stable at
the REGCE input of the block RAM.
Time after the clock that the output data is stable at the DO outputs
of the block RAM (without output register).
Time after the clock that the output data is stable at the DO outputs
of the block RAM (with output register).
www.xilinx.com
RCKx_x
= Hold time (after clock edge)
(1)
Description
(1)
Block RAM Timing Model
135
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