EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 894
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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- Download datasheet (32Mb)
5–48
Stratix IV Device Handbook Volume 2: Transceivers
f
1
You can use the channel reconfiguration with transmitter PLL select mode along with
the CMU PLL reconfiguration mode only if it is a CMU PLL and not an ATX PLL. You
can first reconfigure the second CMU PLL to the desired data rate using CMU PLL
reconfiguration mode. Then use channel reconfiguration with transmitter PLL select
mode to reconfigure the transceiver channel to listen to the second CMU PLL.
For more information about supported configurations, refer to
Reconfiguration Mode Details” on page 5–19
on page
Channel reconfiguration with transmitter PLL select mode is not applicable to regular
transceiver channels in ×4 and ×8 bonded mode configurations.
For guidelines regarding re-using .mifs, specifying input reference clocks, or using
the logical_tx_pll_sel ports, refer to
For more information about reset, refer to the “Reset Sequence when Using Dynamic
Reconfiguration with the Channel and TX PLL select/reconfig Option” section in the
Reset Control and Power Down in Stratix IV Devices
Blocks Reconfigured in the Channel Reconfiguration with Transmitter PLL Select Mode
The blocks reconfigured in this mode have two types of multiplexers. When you
switch between the CMU PLLs within the same transceiver block, the multiplexer that
is reconfigured is within the transceiver block. It is located in the transmitter channel
path.
5–20.
“Special Guidelines” on page
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
and
chapter.
“Memory Initialization File (.mif)”
Dynamic Reconfiguration Modes Implementation
February 2011 Altera Corporation
“Transceiver Channel
5–56.
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