EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 68

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

3–12
Figure 3–10. Simple Dual-Port Timing Waveforms
Figure 3–11. Mixed-Port Read-During-Write Timing Waveforms
Stratix IV Device Handbook Volume 1
q (asynch)
q (asynch)
wraddress
wraddress
rdaddress
rdaddress
wrclock
wrclock
rdclock
rdclock
wren
data
wren
data
rden
rden
din-1
doutn-1
din-1
doutn-1
an-1
an-1
Figure 3–10
dual-port mode with unregistered outputs. Registering the RAM outputs simply
delays the q output by one clock cycle.
Figure 3–11
mode with unregistered outputs.
bn
bn
an
an
din
din
shows timing waveforms for read and write operations in mixed-port
shows timing waveforms for read and write operations in simple
doutn
doutn
b0
b0
a0
a0
a1
a1
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
dout0
dout0
a2
b1
a2
b1
a3
a3
din4
din4
b2
b2
a4
a4
February 2011 Altera Corporation
din5
din5
a5
a5
b3
b3
a6
a6
din6
din6
Memory Modes