EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 1036

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

2–18
Table 2–3. Device Specific Parameters
Table 2–4. Configuring the Transceiver
Stratix IV Device Handbook Volume 3
Do the parameters meet the fibre channel protocol
electrical requirements?
Are three transceiver channels available?
Is there support for 4.25 Gbps and 1.0625 Gbps data
rates?
Is the 8B/10B encoder in the PCS block fibre channel
compliant?
Is there a workaround?
Is the clock rate compensation block in the PCS available
without an 8B/10B encoder?
Phase 1—Architecture
f
In this phase, check whether the Stratix IV GX device supports or meets your design
requirements.
Device Specification
Consider the questions listed in
For the maximum data rates supported, refer to the “Transceiver Performance
Specifications” section in the
chapter.
Transceiver Configuration
The fibre channel protocol uses an 8B/10B encoder and requires clock rate
compensation.
Functional Blocks
Consider the questions listed in
Questions
Questions
DC and Switching Characteristics for Stratix IV Devices
No
The fibre channel protocol consists of two different
End-of-Frame (EOFt) ordered sets. The correct EOFt ordered
set sent by the user logic depends on the ending disparity of
the word preceeding the EOFt. The Stratix IV GX transceiver
does not provide running disparity flags to the user logic.
Therefore, the user logic might not be able to select the
correct EOFt ordered set.
Yes
Implement the 8B/10B encoder in the FPGA fabric.
No
You can implement this in the FPGA fabric.
Yes
For more information, refer to the “Transceiver Performance
Characteristics” section in the
Characteristics for Stratix IV Devices
Yes
Yes
Two CMU PLLs are available within each transceiver block to
support two different transmitter data rates. Each receiver
channel contains a dedicated receiver CDR that supports
4.25 Gbps and 1.0625 Gbps data rates.
Table 2–3
Table 2–4
Chapter 2: Transceiver Design Flow Guide for Stratix IV Devices
before setting device-specific parameters.
before configuring the transceiver.
Example 1: Fibre Channel Protocol Application
Answer
Answer
DC and Switching
February 2011 Altera Corporation
chapter