EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 660
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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1–216
Table 1–74. Stratix IV GX and GT ALTGX Megafunction Ports: Receiver Ports (Part 5 of 7)
Stratix IV Device Handbook Volume 2: Transceivers
rx_runningdisp
Byte Ordering Block
rx_enabyteord
rx_
byteorderalignstatus
Receiver Phase Compensation FIFO
rx_dataout
rx_clkout
Port Name
Output
Output
Output
Output
Output
Input/
Input
coreclkout for
coreclkout for
coreclkout for
Synchronous to
Synchronous to
Synchronous to
rx_clkout or
rx_clkout or
rx_clkout or
rx_clkout for
bonded modes
rx_clkout for
bonded modes
rx_clkout for
bonded modes
Asynchronous
Clock Domain
coreclkout.
coreclkout.
coreclkout.
non-bonded
non-bonded
non-bonded
Clock signal
modes.
modes.
modes.
signal
8B/10B running disparity indicator.
■
■
■
■
Enable byte ordering control.
■
■
Byte ordering status indicator.
■
■
Parallel data output from the receiver to the
FPGA fabric.
■
Recovered clock from the receiver channel.
■
Available in configurations with the 8B/10B
decoder.
A high level—the data on the rx_dataout
port was received with a negative running
disparity.
A low level—the data on the rx_dataout
port was received with a positive running
disparity.
Channel Width:
8—rx_runningdisp = 1
16—rx_runningdisp = 2
32—rx_runningdisp = 4
Available in configurations with the byte
ordering block enabled. The byte ordering
block is rising-edge sensitive to this signal.
A low-to-high transition triggers the byte
ordering block to restart the byte ordering
operation.
Available in configurations with the byte
ordering block enabled.
A high level—the byte ordering block has
detected the programmed byte ordering
pattern in the LSByte of the received data
from the byte deserializer.
The bus width depends on the channel width
multiplied by the number of channels per
instance.
Available only when the rate match FIFO is
not used in the receiver datapath.
Chapter 1: Transceiver Architecture in Stratix IV Devices
Description
February 2011 Altera Corporation
Transceiver Port Lists
Channel
Channel
Channel
Channel
Channel
Scope
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