EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 869
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
Figure 5–13. .mif Instantiation in the User Design
February 2011 Altera Corporation
SONET OC48 RAM
SONET OC48
GIGE RAM
GIGE .mif
.mif
To reconfigure the transceiver channel or CMU PLL, you must configure the required
settings for the transceiver channel or CMU PLL in the ALTGX MegaWizard Plug-In
Manager and compile the ALTGX instance. The dynamic reconfiguration controller
requires that you write these configured settings through the .mif into the transceiver
channel or CMU PLL (using the write_all and reconfig_data[15:0] signals). The
maximum possible size of the .mif is 59 words. Each word contains legal register
settings of the transceiver channel stored in 16 bits. reconfig_address_out[5:0]
provides the address (location) of the 16-bit word in the .mif.
Table 5–6
Table 5–6. .mif Size for the ALTGX Configuration
You can store these .mifs in on-chip or off-chip memory.
Store the .mif in on-chip or off-chip memory and connect it to the dynamic
reconfiguration controller, as shown in
When applying a .mif in the user design, be sure to:
■
■
■
Duplex (Receiver and Transmitter) + Central
control unit
Duplex (Receiver and Transmitter)
Receiver only
Transmitter only
Note to
(1) Each word in the .mif is 16 bits wide.
Use the RAM: 1-PORT megafunction to instantiate a memory block.
Choose the size of the memory block based on the size of the .mif generated.
Instantiate the .mif in the memory block.
Applying a .mif in the User Design
Table
lists the .mif size depending on the ALTGX configuration.
ALTGX Configuration
5–6:
Reconfiguration
User Logic
ALTGX_RECONFIG
Instance
Figure
.mif Size in Words
5–13.
Stratix IV Device Handbook Volume 2: Transceivers
60
55
37
19
SONET OC48 channel
(1)
ALTGX Instances
GIGE channel
PMA Direct Mode
33
28
14
15
5–23
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