EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 69
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Memory Modes
February 2011 Altera Corporation
True Dual-Port Mode
Stratix IV M9K and M144K blocks support true dual-port mode. Sometimes called
bi-directional dual-port, this mode allows you to perform any combination of two
port operations: two reads, two writes, or one read and one write at two different
clock frequencies.
Figure 3–12
Figure 3–12. Stratix IV True Dual-Port Memory
Note to
(1) True dual-port memory supports input/output clock mode in addition to independent clock mode.
The widest bit configuration of the M9K and M144K blocks in true dual-port mode is
as follows:
■
■
Wider configurations are unavailable because the number of output drivers is
equivalent to the maximum bit width of the respective memory block. Because true
dual-port RAM has outputs on two ports, its maximum width equals half of the total
number of output drivers.
configurations in true dual-port mode.
Table 3–7. M9K Block Mixed-Width Configuration (True Dual-Port Mode)
8K × 1
4K × 2
2K × 4
1K × 8
512 × 16
1K × 9
512 × 18
M9K: 512 × 16-bit (or 512 ×18-bit with parity)
M144K: 4K × 32-bit (or 4K ×36-bit with parity)
Read Port
Figure
3–12:
shows the true dual-port RAM configuration.
8K × 1
v
v
v
v
v
—
—
Table 3–7
data_a[ ]
address_a[ ]
wren_a
byteena_a[]
addressstall_a
rden_a
aclr_a
q_a[]
clock_a
4K × 2
v
v
v
v
v
—
—
lists the possible M9K block mixed-port width
2K × 4
v
v
v
v
v
—
—
(Note 1)
addressstall_b
Write Port
address_b[]
byteena_b[]
data_b[ ]
1K × 8
clock_b
wren_b
rden_b
aclr_b
v
v
v
v
v
—
—
q_b[]
Stratix IV Device Handbook Volume 1
512 × 16 1K × 9 512 × 18
v
v
v
v
v
—
—
—
—
—
—
—
v
v
—
—
—
—
—
v
v
3–13
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