EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 929

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Controller Port List
Table 5–16. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 8 of 13)
February 2011 Altera Corporation
tx_preemp_2t[4:0]
rx_eqctrl[3:0]
Port Name
(1)
(1)
Output
Input/
Input
Input
This is an optional pre-emphasis write control for the second
post-tap for the transmit buffer. This signal controls both
pre-emphasis positive and its inversion. Depending on what value
you set at this input, the controller dynamically writes the value to
the pre-emphasis control register of the transmit buffer.
The width of this signal is fixed to 5 bits if you enable either the Use
'logical_channel_address' port for Analog controls
reconfiguration option or the Use same control signal for all the
channels option in the Analog controls screen. Otherwise, the
width of this signal is 5 bits per channel.
For more information, refer to
Controls” on page
The following values are the legal settings allowed for this signal:
0 represents 0
1-15 represents -15 to -1
16 represents 0
17-31 represents 1 to 15
In the PCIe configuration, set tx_preemp_2t[4:0] to 5'b00000
when you do a rate switch from Gen 1 mode to Gen 2 mode. This is
to ensure that tx_preemp_2t[4:0] does not add to the signal
boost when tx_pipemargin and tx_pipedeemph take affect in
PCIe Gen 2 mode.
For more information, refer to the “Programmable Pre-Emphasis”
section of the
This is an optional write control to write an equalization control
value for the receive side of the PMA.
The width of this signal is fixed to 4 bits if you enable either the Use
'logical_channel_address' port for Analog controls
reconfiguration option or the Use same control signal for all the
channels option in the Analog controls screen. Otherwise, the
width of this signal is 4 bits per channel.
For more information, refer to
Controls” on page 5–13
DC Gain” section of the
Devices
chapter.
Transceiver Architecture in Stratix IV Devices
5–13.
Transceiver Architecture in Stratix IV
and the “Programmable Equalization and
Stratix IV Device Handbook Volume 2: Transceivers
Description
“Dynamically Reconfiguring PMA
“Dynamically Reconfiguring PMA
(Note
3),
chapter.
(4)
5–83