EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 594

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

1–150
Figure 1–119. Low-Speed Parallel Clock Switching in PCIe ×8 Mode
Stratix IV Device Handbook Volume 2: Transceivers
Low-Speed Parallel Clock
pipephydonestatus[0]
pipephydonestatus[7]
1
rateswitch
Figure 1–119
Gen2 (500 MHz) in response to the change in the logic level on the rateswitch signal.
The rateswitch completion is shown marked with a one clock cycle assertion of the
pipephydonestatus signal of all eight bonded channels.
Time T1 from a transition on the rateswitch signal to the assertion of
pipephydonestatus is pending characterization.
As a result of the signaling rateswitch between Gen1 (2.5 Gbps) and Gen2 (5 Gbps),
the FPGA fabric-transceiver interface clock switches between 125 MHz and 250 MHz.
The FPGA fabric-transceiver interface clock clocks the read side and write side of the
transmitter phase compensation FIFO and the receiver phase compensation FIFO of
all eight bonded channels, respectively. It is also routed to the FPGA fabric on a global
or regional clock resource and looped back to clock the write port and read port of the
transmitter phase compensation FIFO and the receiver phase compensation FIFO,
respectively. Due to the routing delay between the write and read clock of the
transmitter and receiver phase compensation FIFOs, the write pointers and read
pointers might collide during a rateswitch between 125 MHz and 250 MHz. To avoid
collision of the phase compensation FIFO pointers, the PCIe rateswitch controller
automatically disables and resets the phase compensation FIFO pointers of all eight
bonded channels during clock switch. When the PCIe clock switch circuitry in the
local clock divider indicates successful clock switch completion, the PCIe rateswitch
controller releases the phase compensation FIFO pointer resets.
The PCIe Base Specification 2.0 defines the following three types of conventional
resets to the PCIe system components:
■
■
■
Cold reset—fundamental reset after power up
Warm reset—fundamental reset without removal and re-application of power
Hot reset—In-band conventional reset initiated by the higher layer by setting the
Hot Reset bit in the TS1 or TS2 training sequences
PCIe Cold Reset Requirements
250 MHz (Gen1)
shows the low-speed parallel clock switch between Gen1 (250 MHz) and
T1
500 MHz (Gen2)
Chapter 1: Transceiver Architecture in Stratix IV Devices
T1
February 2011 Altera Corporation
Transceiver Block Architecture
250 MHz (Gen1)