EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 739
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EP4SE530H35C2N
Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SE530H35C2N
Manufacturer:
ALTERA
Quantity:
147
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Chapter 2: Transceiver Clocking in Stratix IV Devices
FPGA Fabric-Transceiver Interface Clocking
February 2011 Altera Corporation
Limitations of the Quartus II Software-Selected Receiver Phase Compensation FIFO Read
Clock
In non-bonded channel configurations without rate matcher, the Quartus II software
cannot determine if the incoming serial data in all channels has a 0 PPM frequency
difference. The Quartus II software uses the recovered clock rx_clkout signal from
each channel to clock the read port of its receiver phase compensation FIFO. This
results in one global, regional, or global and regional clock resource being used per
channel for the rx_clkout signal.
Figure 2–36
across four transceiver blocks. The incoming serial data to all 16 channels have a
0 PPM frequency difference with respect to each other. The Quartus II software uses
rx_clkout from each channel to clock the read port of its receiver phase compensation
FIFO. This results in 16 global, regional, or global and regional clock resources being
used, one for each channel.
Example 7: Sixteen Channels Across Four Transceiver Blocks
shows 16 non-bonded receiver channels without rate matcher, located
Stratix IV Device Handbook Volume 2: Transceivers
2–67
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