EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 62
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
EP4SE530H35C2N
Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SE530H35C2N
Manufacturer:
ALTERA
Quantity:
147
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SE230F29C3N PDF datasheet #6
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- Download datasheet (32Mb)
3–6
Figure 3–5. Output Latch Asynchronous Clear Waveform
Stratix IV Device Handbook Volume 1
Mixed Width Support
Asynchronous Clear
aclr at latch
outclk
aclr
f
1
q
Figure 3–4
Figure 3–4. Address Clock Enable During the Write Cycle Waveform
M9K and M144K memory blocks support mixed data widths inherently. MLABs can
support mixed data widths through emulation using the Quartus II software. When
using simple dual-port, true dual-port, or FIFO modes, mixed width support allows
you to read and write different data widths to a memory block. For more information
about the different widths supported per memory mode, refer to
on page
MLABs do not support mixed-width FIFO mode.
Stratix IV TriMatrix memory blocks support asynchronous clears on output latches
and output registers. Therefore, if your RAM is not using output registers, you can
still clear the RAM outputs using the output latch asynchronous clear.
shows a waveform of the output latch asynchronous clear function.
You can selectively enable asynchronous clears per logical memory using the
Quartus II RAM MegaWizard Plug-In Manager.
For more information, refer to the
latched address
(inside memory)
contents at a0
contents at a1
contents at a2
contents at a3
contents at a4
contents at a5
3–8.
addressstall
wraddress
shows the address clock enable waveform during the write cycle.
inclock
wren
data
an
XX
a0
00
XX
a0
a1
01
Internal Memory (RAM and ROM) User
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
XX
01
02
a2
XX
XX
XX
a1
02
a3
03
00
04
a4
February 2011 Altera Corporation
a4
03
“Memory Modes”
a5
05
04
Figure 3–5
a5
Guide.
05
a6
06
Overview
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