EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 475
EP4SE530H35C2N
Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(72 pages)
6.EP4SE230F29C3N.pdf
(12 pages)
Specifications of EP4SE530H35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SE530H35C2N
Manufacturer:
ALTERA
Quantity:
147
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Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Table 1–12. Transmission Bit Order for the Bit Reversal Feature
February 2011 Altera Corporation
Not enabled (default)
Enabled
Transmitter Bit Reversal
Feature
Transmitter Bit Reversal
Table 1–12
reversal enabled.
Figure 1–27
wide datapath configuration.
Figure 1–27. Transmitter Bit Reversal Operation in Basic Single-Width Mode
For example:
■
■
TX bit reversal option enabled in
the ALTGX MegaWizard
8-bit—D[7:0]rewired to D[0:7]
10-bit— D[9:0]rewired to D[0:9]
lists the transmission bit order with and without the transmitter bit
shows the transmitter bit reversal feature in Basic single-width for a 10-bit
Single-Width Mode
(8- or 10-Bit)
LSB to MSB
MSB to LSB
Output from transmitter PCS
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
For example:
■
■
Stratix IV Device Handbook Volume 2: Transceivers
16-bit—D[15:0]rewired to D[0:15]
20-bit—D[19:0]rewired to D[0:19]
Converted data output to the
transmitter serializer
Double-Width Mode
(16- or 20-Bit)
LSB to MSB
MSB to LSB
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D[8]
D[9]
1–31
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