EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 198

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

6–26
Stratix IV Device Handbook Volume 1
On-Chip Series Termination with Calibration
Stratix IV devices support on-chip series termination with calibration in all banks. The
on-chip series termination calibration circuit compares the total impedance of the I/O
buffer to the external 25- Ω ±1% or 50- Ω ±1% resistors connected to the RUP and RDN
pins and dynamically enables or disables the transistors until they match.
The R
occurs at the end of device configuration. When the calibration circuit finds the
correct impedance, it powers down and stops changing the characteristics of the
drivers.
Figure 6–19. On-Chip Series Termination with Calibration
Table 6–6
without calibration.
Table 6–6. Selectable I/O Standards for On-Chip Series Termination with and Without Calibration
(Part 1 of 2)
3.3-V LVTTL/LVCMOS
2.5-V LVCMOS
1.8-V LVCMOS
1.5-V LVCMOS
1.2-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
S
shown in
I/O Standard
lists the I/O standards that support on-chip series termination with and
Series Termination
Figure 6–19
Stratix IV Driver
V
GND
CCIO
is the intrinsic impedance of the transistors. Calibration
R
R
S
S
Row I/O (Ω)
Z
On-Chip Series Termination Setting
50
25
50
25
50
25
50
50
50
25
50
25
O
On-Chip Termination Support and I/O Termination Schemes
= 50 Ω
Chapter 6: I/O Features in Stratix IV Devices
Receiving
Device
February 2011 Altera Corporation
Column I/O (Ω)
50
25
50
25
50
25
50
25
50
25
50
25
50
25