EP2SGX130GF1508I4 Altera, EP2SGX130GF1508I4 Datasheet - Page 67

IC STRATIX II GX 130K 1508-FBGA

EP2SGX130GF1508I4

Manufacturer Part Number
EP2SGX130GF1508I4
Description
IC STRATIX II GX 130K 1508-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet

Specifications of EP2SGX130GF1508I4

Number Of Logic Elements/cells
132540
Number Of Labs/clbs
6627
Total Ram Bits
6747840
Number Of I /o
734
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1508-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
132540
# I/os (max)
734
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
132540
Ram Bits
6747840
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1508
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2174

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Figure 2–43. ALM in Shared Arithmetic Mode
Note to
(1)
Altera Corporation
October 2007
Inputs dataf0 and dataf1 are available for register packing in shared arithmetic mode.
Figure
datae0
datae1
datab
dataa
datad
datac
2–43:
Adder trees are used in many different applications. For example, the
summation of the partial products in a logic-based multiplier can be
implemented in a tree structure. Another example is a correlator function
that can use a large adder tree to sum filtered data samples in a given time
frame to recover or to de-spread data which was transmitted utilizing
spread spectrum technology. An example of a three-bit add operation
utilizing the shared arithmetic mode is shown in
sum (S[2..0]) and the partial carry (C[2..0]) is obtained using the
LUTs, while the result (R[2..0]) is computed using the dedicated
adders.
4-Input
4-Input
4-Input
4-Input
LUT
LUT
LUT
LUT
shared_arith_out
shared_arith_in
carry_out
carry_in
Stratix II GX Device Handbook, Volume 1
D
D
reg0
reg1
Q
Q
Figure
Stratix II GX Architecture
To general or
To general or
To general or
To general or
local routing
local routing
local routing
local routing
2–44. The partial
2–59

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