EP2SGX130GF1508I4 Altera, EP2SGX130GF1508I4 Datasheet - Page 119
EP2SGX130GF1508I4
Manufacturer Part Number
EP2SGX130GF1508I4
Description
IC STRATIX II GX 130K 1508-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX130GF1508I4
Number Of Logic Elements/cells
132540
Number Of Labs/clbs
6627
Total Ram Bits
6747840
Number Of I /o
734
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1508-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
132540
# I/os (max)
734
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
132540
Ram Bits
6747840
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1508
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2174
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2SGX130GF1508I4N
Manufacturer:
Sunon
Quantity:
1 000
Part Number:
EP2SGX130GF1508I4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Altera Corporation
October 2007
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The IOE in Stratix II GX devices contains a bidirectional I/O buffer, six
registers, and a latch for a complete embedded bidirectional single data
rate or DDR transfer.
The IOE contains two input registers (plus a latch), two output registers,
and two output enable registers. You can use both input registers and the
latch to capture DDR input and both output registers to drive DDR
outputs. Additionally, you can use the output enable (OE) register for fast
clock-to-output enable timing. The negative edge-clocked OE register is
used for DDR SDRAM interfacing. The Quartus II software automatically
duplicates a single OE register that controls multiple output or
bidirectional pins.
Open-drain outputs
DQ and DQS I/O pins
Double data rate (DDR) registers
Figure 2–76
shows the Stratix II GX IOE structure.
Stratix II GX Device Handbook, Volume 1
Stratix II GX Architecture
2–111
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