EP1S80F1020C6 Altera, EP1S80F1020C6 Datasheet - Page 227

• Manufacturer Part Number: EP1S80F1020C6
• Description: IC STRATIX FPGA 80K LE 1020-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S80F1020C6

• Number Of Logic Elements/cells: 79040
• Number Of Labs/clbs: 7904
• Total Ram Bits: 7427520
• Number Of I /o: 773
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Other names: 544-1439; EP1S80F1020C6

Altera Corporation
January 2006
Definition of I/O Skew
I/O skew is defined as the absolute value of the worst-case difference in
clock-to-out times (t
common clock source.
I/O bank skew is made up of the following components:
■
■
Figure 4–5
bank, being fed by a common clock source. The clock can come from an
input pin or from a PLL output.
Figure 4–5. I/O Skew within an I/O Bank
Clock network skews: This is the difference between the arrival times
of the clock at the clock input port of the two IOE registers.
Package skews: This is the package trace length differences between
(I/O pad A to I/O pin A) and (I/O pad B to I/O pin B).
Slow Edge
Common Source of GCLK
shows an example of two IOE registers located in the same
I/O Pin B
Fast Edge
I/O Pin A
I/O Skew
CO
I/O Bank
) between any two output registers fed by a
I/O Skew
Stratix Device Handbook, Volume 1
DC & Switching Characteristics
I/O Pin A
I/O Pin B
4–57