EP1S80F1020C6 Altera, EP1S80F1020C6 Datasheet - Page 198

• Manufacturer Part Number: EP1S80F1020C6
• Description: IC STRATIX FPGA 80K LE 1020-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S80F1020C6

• Number Of Logic Elements/cells: 79040
• Number Of Labs/clbs: 7904
• Total Ram Bits: 7427520
• Number Of I /o: 773
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Other names: 544-1439; EP1S80F1020C6

Timing Model
4–28
Stratix Device Handbook, Volume 1
t
t
t
t
t
t
t
EP1S10
EP1S20
EP1S25
EP1S30
SU
H
CO
LUT
CLR
PRE
CLKHL
Table 4–44. LE Internal Timing Microparameters
Table 4–45. IOE Internal TSU Microparameter by Device Density (Part 1 of 2)
Device
Parameter
t
t
t
t
t
t
t
t
SU_R
SU_C
SU_R
SU_C
SU_R
SU_C
SU_R
SU_C
Symbol
1000
Min
100
100
100
10
t
t
t
t
C4
C8
C16
LOCAL
Table 4–43. Routing Delay Internal Timing Microparameter
Descriptions (Part 2 of 2)
Symbol
-5
76
176
76
76
276
276
76
176
Min
Max
156
366
-5
Delay for a C4 line with average loading; covers a distance of four
LAB rows.
Delay for a C8 line with average loading; covers a distance of eight
LAB rows.
Delay for a C16 line with average loading; covers a distance of 16
LAB rows.
Local interconnect delay, for connections within a LAB, and for the
final routing hop of connections to LABs, DSP blocks, RAM blocks
and I/Os.
Max
1111
Min
100
100
100
10
80
80
80
80
280
280
80
180
-6
Min
Max
176
459
-6
Max
1190
Min
114
114
114
11
80
80
80
80
280
280
80
180
Min
Parameter
-7
-7
Max
202
527
Max
1400
80
80
80
80
280
280
80
180
Min
135
135
135
13
Min
Altera Corporation
-8
-8
Max
Max
238
621
January 2006
ps
ps
ps
ps
ps
ps
ps
ps
Unit
Unit
ps
ps
ps
ps
ps
ps
ps