EP1SGX40DF1020C6N Altera, EP1SGX40DF1020C6N Datasheet - Page 270

• Manufacturer Part Number: EP1SGX40DF1020C6N
• Description: IC STRATIX GX FPGA 40K 1020-FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX40DF1020C6N

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 624
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 41250
• # I/os (max): 624
• Frequency (max): 5GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 41250
• Ram Bits: 3423744
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

DLL Jitter
DLL Jitter
6–68
Stratix GX Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
(4)
(5)
t
t
t
m
l0, l1, g0
t
DUTY
JITTER
LOCK
ARESET
Table 6–92. Fast PLL Specifications for -7 & -8 Speed Grades (Part 2 of 2)
See
When using the SERDES, high-speed differential I/O mode supports a maximum output frequency of 210 MHz
to the global or regional clocks (that is, the maximum data rate 840 Mbps divided by the smallest SERDES J factor
of 4).
This parameter is for high-speed differential I/O mode only.
These counters have a maximum of 32 if programmed for 50/50 duty cycle. Otherwise, they have a maximum
of 16.
High-speed differential I/O mode supports W = 1 to 16 and J = 4, 7, 8, or 10.
Symbol
“Maximum Input & Output Clock Rates” on page
Tables 6–91
Duty cycle for DFFIO 1× CLKOUT pin
Period jitter for DIFFIO clock out
Period jitter for internal global or
regional clock
Time required for PLL to acquire lock
Multiplication factors for m counter
Multiplication factors for l0, l1, and g0
counter (4),
Minimum pulse width on
signal
& 6–92:
Table 6–93
circuit.
197 to 200
160 to 196
100 to 159
Table 6–93. DLL Jitter for DQS Phase Shift Reference Circuit
(5)
Parameter
Frequency (MHz)
reports the jitter for the DLL in the DQS phase-shift reference
areset
(3)
(4)
6–54.
(3)
Min
45
10
10
1
1
±100 ps for >200 MHz outclk
±20 mUI for <200 MHz outclk
± 100
± 300
± 500
Max
±80
100
55
32
32
DLL Jitter (ps)
Altera Corporation
June 2006
Integer
Integer
ps or
Unit
mUI
ps
μs
ns
%