EP1SGX40DF1020C6N Altera, EP1SGX40DF1020C6N Datasheet - Page 136

• Manufacturer Part Number: EP1SGX40DF1020C6N
• Description: IC STRATIX GX FPGA 40K 1020-FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX40DF1020C6N

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 624
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 41250
• # I/os (max): 624
• Frequency (max): 5GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 41250
• Ram Bits: 3423744
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

PLLs & Clock Networks
4–70
Stratix GX Device Handbook, Volume 1
Figure 4–41. Global Clock Resources
Regional Clock Network
There are four regional clock networks RCLK[3..0] within each
quadrant of the Stratix GX device that are driven by the same dedicated
CLK[7..0] and CLK[15..12] input pins, PLL outputs, or transceiver
clocks. The regional clock networks only pertain to the quadrant they
drive into. The regional clock networks provide the lowest clock delay
and skew for logic contained within a single quadrant. The CLK clock pins
symmetrically drive the RCLK networks within a particular quadrant, as
shown in
CLK[3..0]
Figure
4–42.
CLK[7..4]
Global Clock [15..0]
CLK[15..12]
Altera Corporation
February 2005
Transceiver
Clocks