EP1SGX40DF1020C6N Altera, EP1SGX40DF1020C6N Datasheet - Page 110
EP1SGX40DF1020C6N
Manufacturer Part Number
EP1SGX40DF1020C6N
Description
IC STRATIX GX FPGA 40K 1020-FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX40DF1020C6N
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
624
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix GX
Number Of Logic Blocks/elements
41250
# I/os (max)
624
Frequency (max)
5GHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.5V
Logic Cells
41250
Ram Bits
3423744
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1SGX40DF1020C6N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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TriMatrix Memory
Figure 4–25. Input/Output Clock Mode in Simple Dual-Port Mode
Note to
(1)
4–44
Stratix GX Device Handbook, Volume 1
All registers shown except the rden register have asynchronous clear ports.
Figure
wraddress[ ]
address[ ]
byteena[ ]
outclken
wrclock
inclken
rdclock
data[ ]
wren
rden
4–25:
8 LAB Row
Clocks
8
Read/Write Clock Mode
The memory blocks implement read/write clock mode for simple dual-
port memory. You can use up to two clocks in this mode. The write clock
controls the block’s data inputs, wraddress, and wren. The read clock
controls the data output, rdaddress, and rden. The memory blocks
support independent clock enables for each clock and asynchronous clear
signals for the read- and write-side registers.
memory block in read/write clock mode.
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
D
ENA
Q
Q
Q
Q
Q
Q
Generator
Pulse
Write
Data In
Read Address
Byte Enable
Write Address
Read Enable
Write Enable
Memory Block
Data Out
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
256 ´ 16
512 ´ 8
Note (1)
D
ENA
Figure 4–26
Q
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