EP1SGX40DF1020C6N Altera, EP1SGX40DF1020C6N Datasheet - Page 140
EP1SGX40DF1020C6N
Manufacturer Part Number
EP1SGX40DF1020C6N
Description
IC STRATIX GX FPGA 40K 1020-FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX40DF1020C6N
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
624
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix GX
Number Of Logic Blocks/elements
41250
# I/os (max)
624
Frequency (max)
5GHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.5V
Logic Cells
41250
Ram Bits
3423744
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1SGX40DF1020C6N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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PLLs & Clock Networks
Figure 4–45. Regional Clock Bus
4–74
Stratix GX Device Handbook, Volume 1
Fast Regional Clock Network [1..0]
Regional Clock Network [3..0]
Global Clock Network [15..0]
IOE clocks have horizontal and vertical block regions that are clocked by
eight I/O clock signals chosen from the 22-quadrant or half-quadrant
clock resources.
quadrant relationship to the I/O clock regions, respectively. The vertical
regions (column pins) have less clock delay than the horizontal regions
(row pins).
Figures 4–46
or Half-Quadrant
Clocks Available
to a Quadrant
Clock [21:0]
and
4–47
show the quadrant and half-
Vertical I/O Cell
IO_CLK[7..0]
Lab Row Clock [7..0]
Horizontal I/O
Cell IO_CLK[7..0]
Altera Corporation
February 2005
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