EP1SGX40DF1020C6N Altera, EP1SGX40DF1020C6N Datasheet - Page 27

• Manufacturer Part Number: EP1SGX40DF1020C6N
• Description: IC STRATIX GX FPGA 40K 1020-FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX40DF1020C6N

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 624
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 41250
• # I/os (max): 624
• Frequency (max): 5GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 41250
• Ram Bits: 3423744
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Altera Corporation
June 2006
The CRU has a built-in switchover circuit to select whether the
voltage-controlled oscillator of the PLL is trained by the reference clock or
the data. The optional port rx_freqlocked monitors when the CRU is
in locked to data mode.
In the automatic mode, the following conditions must be met for the CRU
to switch from locked to reference to locked to data mode:
■
■
The automatic switchover circuit can be overridden by using the optional
ports rx_lockedtorefclk and rx_locktodata.
possible combinations of these two signals.
If the rx_lockedtorefclk and rx_locktodata ports are not used,
the default is auto mode.
Note to
(1)
Multiplication factor (W)
PPM detector
Bandwidth
Run length detector
Table 2–5. Receiver PLL & CRU Adjustable Parameters (Part 2 of 2)
Table 2–6. Possible Combinations of rx_lockedtorefclk & rx_locktodata
The CRU PLL is within the prescribed PPM frequency threshold
setting (125 PPM, 250 PPM, 500 PPM, 1,000 PPM) of the CRU
reference clock.
The reference clock and CRU PLL output are phase matched (phases
are within .08 UI).
Multiplication factors 2, 4, and 5 can only be achieved with the use of the pre-
divider on the
from the transmitter PLL.
Table
rx_locktodata
2–5:
0
0
1
REFCLKB
port or if the CRU is trained with the low speed clock
rx_lockedtorefclk
10-bit or 20-bit mode: 5 to 160 in steps of
8-bit or 16-bit mode: 4 to 128 in steps of 4
Stratix GX Device Handbook, Volume 1
0
1
x
2, 4, 5, 8, 10, 16, or 20
125, 250, 500, 1,000
Low, medium, high
Stratix GX Transceivers
Table 2–6
5
VCO (lock to mode)
Reference CLK
DATA
Auto
shows the
(1)
2–17