EP1S10F780I6N Altera, EP1S10F780I6N Datasheet - Page 593

• Manufacturer Part Number: EP1S10F780I6N
• Description: IC STRATIX FPGA 10K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S10F780I6N

• Number Of Logic Elements/cells: 10570
• Number Of Labs/clbs: 1057
• Total Ram Bits: 920448
• Number Of I /o: 426
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Figure 7–8. Coefficient Loading Schedule in a TDM Filter
Altera Corporation
September 2004
2x clock
1x clock
load h(1), h(3), h(5), h(7)
Cycle 0
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
load h(0), h(2), h(4), h(6)
flops corresponding to h(0), h(2), h(4) and h(6) are enabled. This produces
the temporary output, y
output, y(n). The following shows what the overall output, y(n), equals:
This is identical to the output of the 8-tap filter shown in
cycle 1, this process is repeated at every cycle.
y n
y n
Cycle 1
=
=
+ x n 4
y
x 0 h 0
0
+
y
load h(1), h(3), h(5), h(7)
1
–
+
h 4
Cycle 2
x n 1
1
, which is added to y
+
–
x n 5
h 1
–
load h(0), h(2), h(4), h(6)
+
h 5
x n 2
Stratix Device Handbook, Volume 2
Cycle 3
+
–
x n 6
0
h 2
to produce the overall
–
+
h 6
x n 3
load h(1), h(3), h(5), h(7)
Figure
+
–
x n 7
Cycle 4
h 3
–
7–2. After
h 7
7–15